1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/arch/immap_lsch2.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct serdes_config {
12*4882a593Smuzhiyun u32 protocol;
13*4882a593Smuzhiyun u8 lanes[SRDS_MAX_LANES];
14*4882a593Smuzhiyun };
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun static struct serdes_config serdes1_cfg_tbl[] = {
17*4882a593Smuzhiyun {0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
18*4882a593Smuzhiyun {0x0008, {NONE, NONE, NONE, SATA1} },
19*4882a593Smuzhiyun {0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
20*4882a593Smuzhiyun {0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
21*4882a593Smuzhiyun {0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
22*4882a593Smuzhiyun {0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
23*4882a593Smuzhiyun {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
24*4882a593Smuzhiyun {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
25*4882a593Smuzhiyun {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
26*4882a593Smuzhiyun {}
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static struct serdes_config *serdes_cfg_tbl[] = {
30*4882a593Smuzhiyun serdes1_cfg_tbl,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)33*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct serdes_config *ptr;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
38*4882a593Smuzhiyun return 0;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
41*4882a593Smuzhiyun while (ptr->protocol) {
42*4882a593Smuzhiyun if (ptr->protocol == cfg)
43*4882a593Smuzhiyun return ptr->lanes[lane];
44*4882a593Smuzhiyun ptr++;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun return 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)50*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun int i;
53*4882a593Smuzhiyun struct serdes_config *ptr;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ptr = serdes_cfg_tbl[serdes];
59*4882a593Smuzhiyun while (ptr->protocol) {
60*4882a593Smuzhiyun if (ptr->protocol == prtcl)
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun ptr++;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun if (!ptr->protocol)
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
69*4882a593Smuzhiyun if (ptr->lanes[i] != NONE)
70*4882a593Smuzhiyun return 1;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75