1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2017 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/bitops.h> 9*4882a593Smuzhiyun #include <asm/armv7m.h> 10*4882a593Smuzhiyun #include <asm/armv7m_mpu.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define V7M_MPU_CTRL_ENABLE (1 << 0) 14*4882a593Smuzhiyun #define V7M_MPU_CTRL_DISABLE (0 << 0) 15*4882a593Smuzhiyun #define V7M_MPU_CTRL_HFNMIENA (1 << 1) 16*4882a593Smuzhiyun #define VALID_REGION (1 << 4) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define ENABLE_REGION (1 << 0) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AP_SHIFT 24 21*4882a593Smuzhiyun #define XN_SHIFT 28 22*4882a593Smuzhiyun #define TEX_SHIFT 19 23*4882a593Smuzhiyun #define S_SHIFT 18 24*4882a593Smuzhiyun #define C_SHIFT 17 25*4882a593Smuzhiyun #define B_SHIFT 16 26*4882a593Smuzhiyun #define REGION_SIZE_SHIFT 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CACHEABLE (1 << C_SHIFT) 29*4882a593Smuzhiyun #define BUFFERABLE (1 << B_SHIFT) 30*4882a593Smuzhiyun #define SHAREABLE (1 << S_SHIFT) 31*4882a593Smuzhiyun disable_mpu(void)32*4882a593Smuzhiyunvoid disable_mpu(void) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun writel(0, &V7M_MPU->ctrl); 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun enable_mpu(void)37*4882a593Smuzhiyunvoid enable_mpu(void) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Make sure new mpu config is effective for next memory access */ 42*4882a593Smuzhiyun dsb(); 43*4882a593Smuzhiyun isb(); /* Make sure instruction stream sees it */ 44*4882a593Smuzhiyun } 45*4882a593Smuzhiyun mpu_config(struct mpu_region_config * reg_config)46*4882a593Smuzhiyunvoid mpu_config(struct mpu_region_config *reg_config) 47*4882a593Smuzhiyun { 48*4882a593Smuzhiyun uint32_t attr; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun switch (reg_config->mr_attr) { 51*4882a593Smuzhiyun case STRONG_ORDER: 52*4882a593Smuzhiyun attr = SHAREABLE; 53*4882a593Smuzhiyun break; 54*4882a593Smuzhiyun case SHARED_WRITE_BUFFERED: 55*4882a593Smuzhiyun attr = BUFFERABLE; 56*4882a593Smuzhiyun break; 57*4882a593Smuzhiyun case O_I_WT_NO_WR_ALLOC: 58*4882a593Smuzhiyun attr = CACHEABLE; 59*4882a593Smuzhiyun break; 60*4882a593Smuzhiyun case O_I_WB_NO_WR_ALLOC: 61*4882a593Smuzhiyun attr = CACHEABLE | BUFFERABLE; 62*4882a593Smuzhiyun break; 63*4882a593Smuzhiyun case O_I_NON_CACHEABLE: 64*4882a593Smuzhiyun attr = 1 << TEX_SHIFT; 65*4882a593Smuzhiyun break; 66*4882a593Smuzhiyun case O_I_WB_RD_WR_ALLOC: 67*4882a593Smuzhiyun attr = (1 << TEX_SHIFT) | CACHEABLE | BUFFERABLE; 68*4882a593Smuzhiyun break; 69*4882a593Smuzhiyun case DEVICE_NON_SHARED: 70*4882a593Smuzhiyun attr = (2 << TEX_SHIFT) | BUFFERABLE; 71*4882a593Smuzhiyun break; 72*4882a593Smuzhiyun default: 73*4882a593Smuzhiyun attr = 0; /* strongly ordered */ 74*4882a593Smuzhiyun break; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun writel(reg_config->start_addr | VALID_REGION | reg_config->region_no, 78*4882a593Smuzhiyun &V7M_MPU->rbar); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun writel(reg_config->xn << XN_SHIFT | reg_config->ap << AP_SHIFT | attr 81*4882a593Smuzhiyun | reg_config->reg_size << REGION_SIZE_SHIFT | ENABLE_REGION 82*4882a593Smuzhiyun , &V7M_MPU->rasr); 83*4882a593Smuzhiyun } 84