1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2014 3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch-stv0991/hardware.h> 11*4882a593Smuzhiyun #include <asm/arch-stv0991/stv0991_cgu.h> 12*4882a593Smuzhiyun #include <asm/arch-stv0991/stv0991_gpt.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ 15*4882a593Smuzhiyun (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING) 18*4882a593Smuzhiyun #define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define timestamp gd->arch.tbl 23*4882a593Smuzhiyun #define lastdec gd->arch.lastinc 24*4882a593Smuzhiyun timer_init(void)25*4882a593Smuzhiyunint timer_init(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun /* Timer1 clock configuration */ 28*4882a593Smuzhiyun writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq); 29*4882a593Smuzhiyun writel(readl(&stv0991_cgu_regs->cgu_enable_2) | 30*4882a593Smuzhiyun TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Stop the timer */ 33*4882a593Smuzhiyun writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); 34*4882a593Smuzhiyun writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc); 35*4882a593Smuzhiyun /* Configure timer for auto-reload */ 36*4882a593Smuzhiyun writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD, 37*4882a593Smuzhiyun &gpt1_regs_ptr->cr1); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* load value for free running */ 40*4882a593Smuzhiyun writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* start timer */ 43*4882a593Smuzhiyun writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, 44*4882a593Smuzhiyun &gpt1_regs_ptr->cr1); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Reset the timer */ 47*4882a593Smuzhiyun lastdec = READ_TIMER(); 48*4882a593Smuzhiyun timestamp = 0; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun return 0; 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * timer without interrupts 55*4882a593Smuzhiyun */ get_timer(ulong base)56*4882a593Smuzhiyunulong get_timer(ulong base) 57*4882a593Smuzhiyun { 58*4882a593Smuzhiyun return (get_timer_masked() / GPT_RESOLUTION) - base; 59*4882a593Smuzhiyun } 60*4882a593Smuzhiyun __udelay(unsigned long usec)61*4882a593Smuzhiyunvoid __udelay(unsigned long usec) 62*4882a593Smuzhiyun { 63*4882a593Smuzhiyun ulong tmo; 64*4882a593Smuzhiyun ulong start = get_timer_masked(); 65*4882a593Smuzhiyun ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100); 66*4882a593Smuzhiyun ulong rndoff; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun rndoff = (usec % 10) ? 1 : 0; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* tenudelcnt timer tick gives 10 microsecconds delay */ 71*4882a593Smuzhiyun tmo = ((usec / 10) + rndoff) * tenudelcnt; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun while ((ulong) (get_timer_masked() - start) < tmo) 74*4882a593Smuzhiyun ; 75*4882a593Smuzhiyun } 76*4882a593Smuzhiyun get_timer_masked(void)77*4882a593Smuzhiyunulong get_timer_masked(void) 78*4882a593Smuzhiyun { 79*4882a593Smuzhiyun ulong now = READ_TIMER(); 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun if (now >= lastdec) { 82*4882a593Smuzhiyun /* normal mode */ 83*4882a593Smuzhiyun timestamp += now - lastdec; 84*4882a593Smuzhiyun } else { 85*4882a593Smuzhiyun /* we have an overflow ... */ 86*4882a593Smuzhiyun timestamp += now + GPT_FREE_RUNNING - lastdec; 87*4882a593Smuzhiyun } 88*4882a593Smuzhiyun lastdec = now; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun return timestamp; 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun udelay_masked(unsigned long usec)93*4882a593Smuzhiyunvoid udelay_masked(unsigned long usec) 94*4882a593Smuzhiyun { 95*4882a593Smuzhiyun return udelay(usec); 96*4882a593Smuzhiyun } 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * This function is derived from PowerPC code (read timebase as long long). 100*4882a593Smuzhiyun * On ARM it just returns the timer value. 101*4882a593Smuzhiyun */ get_ticks(void)102*4882a593Smuzhiyununsigned long long get_ticks(void) 103*4882a593Smuzhiyun { 104*4882a593Smuzhiyun return get_timer(0); 105*4882a593Smuzhiyun } 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* 108*4882a593Smuzhiyun * This function is derived from PowerPC code (timebase clock frequency). 109*4882a593Smuzhiyun * On ARM it returns the number of timer ticks per second. 110*4882a593Smuzhiyun */ get_tbclk(void)111*4882a593Smuzhiyunulong get_tbclk(void) 112*4882a593Smuzhiyun { 113*4882a593Smuzhiyun return CONFIG_STV0991_HZ; 114*4882a593Smuzhiyun } 115