1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <asm/arch/stv0991_creg.h>
10*4882a593Smuzhiyun #include <asm/arch/stv0991_periph.h>
11*4882a593Smuzhiyun #include <asm/arch/hardware.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static struct stv0991_creg *const stv0991_creg = \
14*4882a593Smuzhiyun (struct stv0991_creg *)CREG_BASE_ADDR;
15*4882a593Smuzhiyun
stv0991_pinmux_config(int peripheral)16*4882a593Smuzhiyun int stv0991_pinmux_config(int peripheral)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun switch (peripheral) {
19*4882a593Smuzhiyun case UART_GPIOC_30_31:
20*4882a593Smuzhiyun /* SSDA/SSCL pad muxing to UART Rx/Dx */
21*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
22*4882a593Smuzhiyun CFG_GPIOC_31_UART_RX,
23*4882a593Smuzhiyun &stv0991_creg->mux12);
24*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
25*4882a593Smuzhiyun CFG_GPIOC_30_UART_TX,
26*4882a593Smuzhiyun &stv0991_creg->mux12);
27*4882a593Smuzhiyun /* SSDA/SSCL pad config to push pull*/
28*4882a593Smuzhiyun writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
29*4882a593Smuzhiyun CFG_GPIOC_31_MODE_PP,
30*4882a593Smuzhiyun &stv0991_creg->cfg_pad6);
31*4882a593Smuzhiyun writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
32*4882a593Smuzhiyun CFG_GPIOC_30_MODE_HIGH,
33*4882a593Smuzhiyun &stv0991_creg->cfg_pad6);
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun case UART_GPIOB_16_17:
36*4882a593Smuzhiyun /* ethernet rx_6/7 to UART Rx/Dx */
37*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
38*4882a593Smuzhiyun CFG_GPIOB_17_UART_RX,
39*4882a593Smuzhiyun &stv0991_creg->mux7);
40*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
41*4882a593Smuzhiyun CFG_GPIOB_16_UART_TX,
42*4882a593Smuzhiyun &stv0991_creg->mux7);
43*4882a593Smuzhiyun break;
44*4882a593Smuzhiyun case ETH_GPIOB_10_31_C_0_4:
45*4882a593Smuzhiyun writel(readl(&stv0991_creg->mux6) & 0x000000FF,
46*4882a593Smuzhiyun &stv0991_creg->mux6);
47*4882a593Smuzhiyun writel(0x00000000, &stv0991_creg->mux7);
48*4882a593Smuzhiyun writel(0x00000000, &stv0991_creg->mux8);
49*4882a593Smuzhiyun writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
50*4882a593Smuzhiyun &stv0991_creg->mux9);
51*4882a593Smuzhiyun /* Ethernet Voltage configuration to 1.8V*/
52*4882a593Smuzhiyun writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
53*4882a593Smuzhiyun ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
54*4882a593Smuzhiyun writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
55*4882a593Smuzhiyun ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun break;
58*4882a593Smuzhiyun case QSPI_CS_CLK_PAD:
59*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
60*4882a593Smuzhiyun CFG_FLASH_CS_NC, &stv0991_creg->mux13);
61*4882a593Smuzhiyun writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
62*4882a593Smuzhiyun CFG_FLASH_CLK, &stv0991_creg->mux13);
63*4882a593Smuzhiyun default:
64*4882a593Smuzhiyun break;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun return 0;
67*4882a593Smuzhiyun }
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