1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010 Samsung Electronics 3*4882a593Smuzhiyun * Naveen Krishna Ch <ch.naveen@samsung.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/sromc.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * s5p_config_sromc() - select the proper SROMC Bank and configure the 14*4882a593Smuzhiyun * band width control and bank control registers 15*4882a593Smuzhiyun * srom_bank - SROM 16*4882a593Smuzhiyun * srom_bw_conf - SMC Band witdh reg configuration value 17*4882a593Smuzhiyun * srom_bc_conf - SMC Bank Control reg configuration value 18*4882a593Smuzhiyun */ s5p_config_sromc(u32 srom_bank,u32 srom_bw_conf,u32 srom_bc_conf)19*4882a593Smuzhiyunvoid s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf) 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun u32 tmp; 22*4882a593Smuzhiyun struct s5p_sromc *srom = 23*4882a593Smuzhiyun (struct s5p_sromc *)samsung_get_base_sromc(); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Configure SMC_BW register to handle proper SROMC bank */ 26*4882a593Smuzhiyun tmp = srom->bw; 27*4882a593Smuzhiyun tmp &= ~(0xF << (srom_bank * 4)); 28*4882a593Smuzhiyun tmp |= srom_bw_conf; 29*4882a593Smuzhiyun srom->bw = tmp; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Configure SMC_BC register */ 32*4882a593Smuzhiyun srom->bc[srom_bank] = srom_bc_conf; 33*4882a593Smuzhiyun } 34