1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
9*4882a593Smuzhiyun #include <asm/arch/immap_ls102xa.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
12*4882a593Smuzhiyun [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1},
13*4882a593Smuzhiyun [0x10] = {PCIE1, SATA1, PCIE2, PCIE2},
14*4882a593Smuzhiyun [0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2},
15*4882a593Smuzhiyun [0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2},
16*4882a593Smuzhiyun [0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2},
17*4882a593Smuzhiyun [0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2},
18*4882a593Smuzhiyun [0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
19*4882a593Smuzhiyun [0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2},
20*4882a593Smuzhiyun [0x80] = {PCIE2, PCIE2, PCIE2, PCIE2},
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
serdes_get_prtcl(int serdes,int cfg,int lane)23*4882a593Smuzhiyun enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun return serdes_cfg_tbl[cfg][lane];
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
is_serdes_prtcl_valid(int serdes,u32 prtcl)28*4882a593Smuzhiyun int is_serdes_prtcl_valid(int serdes, u32 prtcl)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun int i;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun for (i = 0; i < SRDS_MAX_LANES; i++) {
36*4882a593Smuzhiyun if (serdes_cfg_tbl[prtcl][i] != NONE)
37*4882a593Smuzhiyun return 1;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42