1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #include <common.h> 7*4882a593Smuzhiyun #include <asm/io.h> 8*4882a593Smuzhiyun #include <asm/arch/immap_ls102xa.h> 9*4882a593Smuzhiyun #include <ahci.h> 10*4882a593Smuzhiyun #include <scsi.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* port register default value */ 13*4882a593Smuzhiyun #define AHCI_PORT_PHY_1_CFG 0xa003fffe 14*4882a593Smuzhiyun #define AHCI_PORT_PHY_2_CFG 0x28183414 15*4882a593Smuzhiyun #define AHCI_PORT_PHY_3_CFG 0x0e080e06 16*4882a593Smuzhiyun #define AHCI_PORT_PHY_4_CFG 0x064a080b 17*4882a593Smuzhiyun #define AHCI_PORT_PHY_5_CFG 0x2aa86470 18*4882a593Smuzhiyun #define AHCI_PORT_TRANS_CFG 0x08000029 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define SATA_ECC_REG_ADDR 0x20220520 21*4882a593Smuzhiyun #define SATA_ECC_DISABLE 0x00020000 22*4882a593Smuzhiyun ls1021a_sata_init(void)23*4882a593Smuzhiyunint ls1021a_sata_init(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_ERRATUM_A008407 28*4882a593Smuzhiyun out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); 32*4882a593Smuzhiyun out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); 33*4882a593Smuzhiyun out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); 34*4882a593Smuzhiyun out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); 35*4882a593Smuzhiyun out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); 36*4882a593Smuzhiyun out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun ahci_init((void __iomem *)AHCI_BASE_ADDR); 39*4882a593Smuzhiyun scsi_scan(false); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun return 0; 42*4882a593Smuzhiyun } 43