1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include "fsl_epu.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun struct fsm_reg_vals epu_default_val[] = {
13*4882a593Smuzhiyun /* EPGCR (Event Processor Global Control Register) */
14*4882a593Smuzhiyun {EPGCR, 0},
15*4882a593Smuzhiyun /* EPECR (Event Processor Event Control Registers) */
16*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 0, 0},
17*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 1, 0},
18*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
19*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
20*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
21*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
22*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
23*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
24*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
25*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
26*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
27*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
28*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
29*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
30*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
31*4882a593Smuzhiyun {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * EPEVTCR (Event Processor EVT Pin Control Registers)
34*4882a593Smuzhiyun * SCU8 triger EVT2, and SCU11 triger EVT9
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
37*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
38*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
39*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
40*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
41*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
42*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
43*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
44*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
45*4882a593Smuzhiyun {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
46*4882a593Smuzhiyun /* EPCMPR (Event Processor Counter Compare Registers) */
47*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
48*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
49*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
50*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
51*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
52*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
53*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
54*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
55*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
56*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
57*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
58*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
59*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
60*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
61*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
62*4882a593Smuzhiyun {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
63*4882a593Smuzhiyun /* EPCCR (Event Processor Counter Control Registers) */
64*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 0, 0},
65*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 1, 0},
66*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
67*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 3, 0},
68*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
69*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
70*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 6, 0},
71*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 7, 0},
72*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
73*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
74*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
75*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
76*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
77*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 13, 0},
78*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
79*4882a593Smuzhiyun {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
80*4882a593Smuzhiyun /* EPSMCR (Event Processor SCU Mux Control Registers) */
81*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
82*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
83*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
84*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
85*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
86*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
87*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
88*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
89*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
90*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
91*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
92*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
93*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
94*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
95*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
96*4882a593Smuzhiyun {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
97*4882a593Smuzhiyun /* EPACR (Event Processor Action Control Registers) */
98*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 0, 0},
99*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 1, 0},
100*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 2, 0},
101*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
102*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 4, 0},
103*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
104*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 6, 0},
105*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 7, 0},
106*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 8, 0},
107*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
108*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
109*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 11, 0},
110*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
111*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
112*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
113*4882a593Smuzhiyun {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
114*4882a593Smuzhiyun /* EPIMCR (Event Processor Input Mux Control Registers) */
115*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
116*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
117*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
118*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
119*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
120*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
121*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
122*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
123*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
124*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
125*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
126*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
127*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
128*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
129*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
130*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
131*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
132*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
133*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
134*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
135*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
136*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
137*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
138*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
139*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
140*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
141*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
142*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
143*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
144*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
145*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
146*4882a593Smuzhiyun {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
147*4882a593Smuzhiyun /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
148*4882a593Smuzhiyun {EPXTRIGCR, 0x0000FFDF},
149*4882a593Smuzhiyun /* end */
150*4882a593Smuzhiyun {FSM_END_FLAG, 0},
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /**
154*4882a593Smuzhiyun * fsl_epu_setup - Setup EPU registers to default values
155*4882a593Smuzhiyun */
fsl_epu_setup(void * epu_base)156*4882a593Smuzhiyun void fsl_epu_setup(void *epu_base)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct fsm_reg_vals *data = epu_default_val;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (!epu_base || !data)
161*4882a593Smuzhiyun return;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun while (data->offset != FSM_END_FLAG) {
164*4882a593Smuzhiyun out_be32(epu_base + data->offset, data->value);
165*4882a593Smuzhiyun data++;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun /**
170*4882a593Smuzhiyun * fsl_epu_clean - Clear EPU registers
171*4882a593Smuzhiyun */
fsl_epu_clean(void * epu_base)172*4882a593Smuzhiyun void fsl_epu_clean(void *epu_base)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun u32 offset;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* follow the exact sequence to clear the registers */
177*4882a593Smuzhiyun /* Clear EPACRn */
178*4882a593Smuzhiyun for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
179*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun /* Clear EPEVTCRn */
182*4882a593Smuzhiyun for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
183*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* Clear EPGCR */
186*4882a593Smuzhiyun out_be32(epu_base + EPGCR, 0);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* Clear EPSMCRn */
189*4882a593Smuzhiyun for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
190*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Clear EPCCRn */
193*4882a593Smuzhiyun for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
194*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* Clear EPCMPRn */
197*4882a593Smuzhiyun for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
198*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun /* Clear EPCTRn */
201*4882a593Smuzhiyun for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
202*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun /* Clear EPIMCRn */
205*4882a593Smuzhiyun for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
206*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* Clear EPXTRIGCRn */
209*4882a593Smuzhiyun out_be32(epu_base + EPXTRIGCR, 0);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* Clear EPECRn */
212*4882a593Smuzhiyun for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
213*4882a593Smuzhiyun out_be32(epu_base + offset, 0);
214*4882a593Smuzhiyun }
215