1*4882a593Smuzhiyunconfig ARCH_LS1021A 2*4882a593Smuzhiyun bool 3*4882a593Smuzhiyun select SYS_FSL_ERRATUM_A008378 4*4882a593Smuzhiyun select SYS_FSL_ERRATUM_A008407 5*4882a593Smuzhiyun select SYS_FSL_ERRATUM_A009663 6*4882a593Smuzhiyun select SYS_FSL_ERRATUM_A009942 7*4882a593Smuzhiyun select SYS_FSL_ERRATUM_A010315 8*4882a593Smuzhiyun select SYS_FSL_SRDS_1 9*4882a593Smuzhiyun select SYS_HAS_SERDES 10*4882a593Smuzhiyun select SYS_FSL_DDR_BE if SYS_FSL_DDR 11*4882a593Smuzhiyun select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR 12*4882a593Smuzhiyun select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR 13*4882a593Smuzhiyun select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR 14*4882a593Smuzhiyun select SYS_FSL_HAS_SEC 15*4882a593Smuzhiyun select SYS_FSL_SEC_COMPAT_5 16*4882a593Smuzhiyun select SYS_FSL_SEC_LE 17*4882a593Smuzhiyun imply SCSI 18*4882a593Smuzhiyun imply CMD_PCI 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunmenu "LS102xA architecture" 21*4882a593Smuzhiyun depends on ARCH_LS1021A 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunconfig FSL_PCIE_COMPAT 24*4882a593Smuzhiyun string "PCIe compatible of Kernel DT" 25*4882a593Smuzhiyun depends on PCIE_LAYERSCAPE 26*4882a593Smuzhiyun default "fsl,ls1021a-pcie" if ARCH_LS1021A 27*4882a593Smuzhiyun help 28*4882a593Smuzhiyun This compatible is used to find pci controller node in Kernel DT 29*4882a593Smuzhiyun to complete fixup. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyunconfig LS1_DEEP_SLEEP 32*4882a593Smuzhiyun bool "Deep sleep" 33*4882a593Smuzhiyun depends on ARCH_LS1021A 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig MAX_CPUS 36*4882a593Smuzhiyun int "Maximum number of CPUs permitted for LS102xA" 37*4882a593Smuzhiyun depends on ARCH_LS1021A 38*4882a593Smuzhiyun default 2 39*4882a593Smuzhiyun help 40*4882a593Smuzhiyun Set this number to the maximum number of possible CPUs in the SoC. 41*4882a593Smuzhiyun SoCs may have multiple clusters with each cluster may have multiple 42*4882a593Smuzhiyun ports. If some ports are reserved but higher ports are used for 43*4882a593Smuzhiyun cores, count the reserved ports. This will allocate enough memory 44*4882a593Smuzhiyun in spin table to properly handle all cores. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunconfig SECURE_BOOT 47*4882a593Smuzhiyun bool "Secure Boot" 48*4882a593Smuzhiyun help 49*4882a593Smuzhiyun Enable Freescale Secure Boot feature. Normally selected 50*4882a593Smuzhiyun by defconfig. If unsure, do not change. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A010315 53*4882a593Smuzhiyun bool "Workaround for PCIe erratum A010315" 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunconfig SYS_FSL_SRDS_1 56*4882a593Smuzhiyun bool 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunconfig SYS_FSL_SRDS_2 59*4882a593Smuzhiyun bool 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunconfig SYS_HAS_SERDES 62*4882a593Smuzhiyun bool 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunconfig SYS_FSL_IFC_BANK_COUNT 65*4882a593Smuzhiyun int "Maximum banks of Integrated flash controller" 66*4882a593Smuzhiyun depends on ARCH_LS1021A 67*4882a593Smuzhiyun default 8 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunconfig SYS_FSL_ERRATUM_A008407 70*4882a593Smuzhiyun bool 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunendmenu 73