1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Broadcom Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <div64.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/iproc-common/timer.h>
11*4882a593Smuzhiyun #include <asm/iproc-common/sysmap.h>
12*4882a593Smuzhiyun
timer_global_read(void)13*4882a593Smuzhiyun static inline uint64_t timer_global_read(void)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun uint64_t cur_tick;
16*4882a593Smuzhiyun uint32_t count_h;
17*4882a593Smuzhiyun uint32_t count_l;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun do {
20*4882a593Smuzhiyun count_h = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
21*4882a593Smuzhiyun TIMER_GLB_HI_OFFSET);
22*4882a593Smuzhiyun count_l = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
23*4882a593Smuzhiyun TIMER_GLB_LOW_OFFSET);
24*4882a593Smuzhiyun cur_tick = readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
25*4882a593Smuzhiyun TIMER_GLB_HI_OFFSET);
26*4882a593Smuzhiyun } while (cur_tick != count_h);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return (cur_tick << 32) + count_l;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
timer_global_init(void)31*4882a593Smuzhiyun void timer_global_init(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
34*4882a593Smuzhiyun writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_LOW_OFFSET);
35*4882a593Smuzhiyun writel(0, IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_HI_OFFSET);
36*4882a593Smuzhiyun writel(TIMER_GLB_TIM_CTRL_TIM_EN,
37*4882a593Smuzhiyun IPROC_PERIPH_GLB_TIM_REG_BASE + TIMER_GLB_CTRL_OFFSET);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
timer_init(void)40*4882a593Smuzhiyun int timer_init(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun timer_global_init();
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
get_timer(unsigned long base)46*4882a593Smuzhiyun unsigned long get_timer(unsigned long base)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun uint64_t count;
49*4882a593Smuzhiyun uint64_t ret;
50*4882a593Smuzhiyun uint64_t tim_clk;
51*4882a593Smuzhiyun uint64_t periph_clk;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun count = timer_global_read();
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per msec */
56*4882a593Smuzhiyun periph_clk = 500000;
57*4882a593Smuzhiyun tim_clk = lldiv(periph_clk,
58*4882a593Smuzhiyun (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
59*4882a593Smuzhiyun TIMER_GLB_CTRL_OFFSET) &
60*4882a593Smuzhiyun TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ret = lldiv(count, (uint32_t)tim_clk);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* returns msec */
65*4882a593Smuzhiyun return ret - base;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
__udelay(unsigned long usec)68*4882a593Smuzhiyun void __udelay(unsigned long usec)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun uint64_t cur_tick, end_tick;
71*4882a593Smuzhiyun uint64_t tim_clk;
72*4882a593Smuzhiyun uint64_t periph_clk;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* default arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec */
75*4882a593Smuzhiyun periph_clk = 500;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun tim_clk = lldiv(periph_clk,
78*4882a593Smuzhiyun (((readl(IPROC_PERIPH_GLB_TIM_REG_BASE +
79*4882a593Smuzhiyun TIMER_GLB_CTRL_OFFSET) &
80*4882a593Smuzhiyun TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun cur_tick = timer_global_read();
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun end_tick = tim_clk;
85*4882a593Smuzhiyun end_tick *= usec;
86*4882a593Smuzhiyun end_tick += cur_tick;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun do {
89*4882a593Smuzhiyun cur_tick = timer_global_read();
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun } while (cur_tick < end_tick);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
timer_systick_init(uint32_t tick_ms)94*4882a593Smuzhiyun void timer_systick_init(uint32_t tick_ms)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun /* Disable timer and clear interrupt status*/
97*4882a593Smuzhiyun writel(0, IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
98*4882a593Smuzhiyun writel(TIMER_PVT_TIM_INT_STATUS_SET,
99*4882a593Smuzhiyun IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
100*4882a593Smuzhiyun writel((PLL_AXI_CLK/1000) * tick_ms,
101*4882a593Smuzhiyun IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_LOAD_OFFSET);
102*4882a593Smuzhiyun writel(TIMER_PVT_TIM_CTRL_INT_EN |
103*4882a593Smuzhiyun TIMER_PVT_TIM_CTRL_AUTO_RELD |
104*4882a593Smuzhiyun TIMER_PVT_TIM_CTRL_TIM_EN,
105*4882a593Smuzhiyun IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_CTRL_OFFSET);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
timer_systick_isr(void * data)108*4882a593Smuzhiyun void timer_systick_isr(void *data)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun writel(TIMER_PVT_TIM_INT_STATUS_SET,
111*4882a593Smuzhiyun IPROC_PERIPH_PVT_TIM_REG_BASE + TIMER_PVT_STATUS_OFFSET);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * This function is derived from PowerPC code (read timebase as long long).
116*4882a593Smuzhiyun * On ARM it just returns the timer value in msec.
117*4882a593Smuzhiyun */
get_ticks(void)118*4882a593Smuzhiyun unsigned long long get_ticks(void)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return get_timer(0);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /*
124*4882a593Smuzhiyun * This is used in conjuction with get_ticks, which returns msec as ticks.
125*4882a593Smuzhiyun * Here we just return ticks/sec = msec/sec = 1000
126*4882a593Smuzhiyun */
get_tbclk(void)127*4882a593Smuzhiyun ulong get_tbclk(void)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun return 1000;
130*4882a593Smuzhiyun }
131