1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Broadcom Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <asm/arch/sysmap.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define EN_MASK 0x08000000 /* Enable timer */ 12*4882a593Smuzhiyun #define SRSTEN_MASK 0x04000000 /* Enable soft reset */ 13*4882a593Smuzhiyun #define CLKS_SHIFT 20 /* Clock period shift */ 14*4882a593Smuzhiyun #define LD_SHIFT 0 /* Reload value shift */ 15*4882a593Smuzhiyun reset_cpu(ulong ignored)16*4882a593Smuzhiyunvoid reset_cpu(ulong ignored) 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Set WD enable, RST enable, 20*4882a593Smuzhiyun * 3.9 msec clock period (8), reload value (8*3.9ms) 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun u32 reg = EN_MASK + SRSTEN_MASK + (8 << CLKS_SHIFT) + (8 << LD_SHIFT); 23*4882a593Smuzhiyun writel(reg, SECWD2_BASE_ADDR); 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun while (1) 26*4882a593Smuzhiyun ; /* loop forever till reset */ 27*4882a593Smuzhiyun } 28