1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Broadcom Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/io.h> 9*4882a593Smuzhiyun #include <linux/errno.h> 10*4882a593Smuzhiyun #include <asm/arch/sysmap.h> 11*4882a593Smuzhiyun #include <asm/kona-common/clk.h> 12*4882a593Smuzhiyun #include "clk-core.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Enable appropriate clocks for a BSC/I2C port */ clk_bsc_enable(void * base)15*4882a593Smuzhiyunint clk_bsc_enable(void *base) 16*4882a593Smuzhiyun { 17*4882a593Smuzhiyun int ret; 18*4882a593Smuzhiyun char *bscstr, *apbstr; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun switch ((u32) base) { 21*4882a593Smuzhiyun case PMU_BSC_BASE_ADDR: 22*4882a593Smuzhiyun /* PMU clock is always enabled */ 23*4882a593Smuzhiyun return 0; 24*4882a593Smuzhiyun case BSC1_BASE_ADDR: 25*4882a593Smuzhiyun bscstr = "bsc1_clk"; 26*4882a593Smuzhiyun apbstr = "bsc1_apb_clk"; 27*4882a593Smuzhiyun break; 28*4882a593Smuzhiyun case BSC2_BASE_ADDR: 29*4882a593Smuzhiyun bscstr = "bsc2_clk"; 30*4882a593Smuzhiyun apbstr = "bsc2_apb_clk"; 31*4882a593Smuzhiyun break; 32*4882a593Smuzhiyun case BSC3_BASE_ADDR: 33*4882a593Smuzhiyun bscstr = "bsc3_clk"; 34*4882a593Smuzhiyun apbstr = "bsc3_apb_clk"; 35*4882a593Smuzhiyun break; 36*4882a593Smuzhiyun default: 37*4882a593Smuzhiyun printf("%s: base 0x%p not found\n", __func__, base); 38*4882a593Smuzhiyun return -EINVAL; 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Note that the bus clock must be enabled first */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun ret = clk_get_and_enable(apbstr); 44*4882a593Smuzhiyun if (ret) 45*4882a593Smuzhiyun return ret; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ret = clk_get_and_enable(bscstr); 48*4882a593Smuzhiyun if (ret) 49*4882a593Smuzhiyun return ret; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun return 0; 52*4882a593Smuzhiyun } 53