1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * armboot - Startup Code for ARM926EJS CPU-core 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2003 Texas Instruments 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9*4882a593Smuzhiyun * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10*4882a593Smuzhiyun * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11*4882a593Smuzhiyun * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12*4882a593Smuzhiyun * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13*4882a593Smuzhiyun * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include <asm-offsets.h> 19*4882a593Smuzhiyun#include <config.h> 20*4882a593Smuzhiyun#include <common.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun/* 23*4882a593Smuzhiyun ************************************************************************* 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Startup Code (reset vector) 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * do important init only if we don't start from memory! 28*4882a593Smuzhiyun * setup Memory and board specific bits prior to relocation. 29*4882a593Smuzhiyun * relocate armboot to ram 30*4882a593Smuzhiyun * setup stack 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun ************************************************************************* 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun .globl reset 36*4882a593Smuzhiyun 37*4882a593Smuzhiyunreset: 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * set the cpu to SVC32 mode 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun mrs r0,cpsr 42*4882a593Smuzhiyun bic r0,r0,#0x1f 43*4882a593Smuzhiyun orr r0,r0,#0xd3 44*4882a593Smuzhiyun msr cpsr,r0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * we do sys-critical inits only at reboot, 48*4882a593Smuzhiyun * not when booting from ram! 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT 51*4882a593Smuzhiyun bl cpu_init_crit 52*4882a593Smuzhiyun#endif 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun bl _main 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun/*------------------------------------------------------------------------------*/ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun .globl c_runtime_cpu_setup 59*4882a593Smuzhiyunc_runtime_cpu_setup: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun bx lr 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun/* 64*4882a593Smuzhiyun ************************************************************************* 65*4882a593Smuzhiyun * 66*4882a593Smuzhiyun * CPU_init_critical registers 67*4882a593Smuzhiyun * 68*4882a593Smuzhiyun * setup important registers 69*4882a593Smuzhiyun * setup memory timing 70*4882a593Smuzhiyun * 71*4882a593Smuzhiyun ************************************************************************* 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT 74*4882a593Smuzhiyuncpu_init_crit: 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * flush D cache before disabling it 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun mov r0, #0 79*4882a593Smuzhiyunflush_dcache: 80*4882a593Smuzhiyun mrc p15, 0, r15, c7, c10, 3 81*4882a593Smuzhiyun bne flush_dcache 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 84*4882a593Smuzhiyun mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * disable MMU and D cache 88*4882a593Smuzhiyun * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 91*4882a593Smuzhiyun bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 92*4882a593Smuzhiyun bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 93*4882a593Smuzhiyun#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 94*4882a593Smuzhiyun orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 95*4882a593Smuzhiyun#else 96*4882a593Smuzhiyun bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 97*4882a593Smuzhiyun#endif 98*4882a593Smuzhiyun orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 99*4882a593Smuzhiyun#ifndef CONFIG_SYS_ICACHE_OFF 100*4882a593Smuzhiyun orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 101*4882a593Smuzhiyun#endif 102*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * Go setup Memory and board specific bits prior to relocation. 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun mov ip, lr /* perserve link reg across call */ 109*4882a593Smuzhiyun bl lowlevel_init /* go setup pll,mux,memory */ 110*4882a593Smuzhiyun mov lr, ip /* restore link */ 111*4882a593Smuzhiyun#endif 112*4882a593Smuzhiyun mov pc, lr /* back to my caller */ 113*4882a593Smuzhiyun#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 114