1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * armboot - Startup Code for ARM926EJS CPU-core 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2003 Texas Instruments 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9*4882a593Smuzhiyun * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10*4882a593Smuzhiyun * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11*4882a593Smuzhiyun * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12*4882a593Smuzhiyun * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun#include <config.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/* 21*4882a593Smuzhiyun ************************************************************************* 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * Startup Code (reset vector) 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * Below are the critical initializations already taken place in BootROM. 26*4882a593Smuzhiyun * So, these are not taken care in Xloader 27*4882a593Smuzhiyun * 1. Relocation to RAM 28*4882a593Smuzhiyun * 2. Initializing stacks 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun ************************************************************************* 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun .globl reset 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunreset: 36*4882a593Smuzhiyun/* 37*4882a593Smuzhiyun * Xloader has to return back to BootROM in a few cases. 38*4882a593Smuzhiyun * eg. Ethernet boot, UART boot, USB boot 39*4882a593Smuzhiyun * Saving registers for returning back 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun stmdb sp!, {r0-r12,r14} 42*4882a593Smuzhiyun bl cpu_init_crit 43*4882a593Smuzhiyun/* 44*4882a593Smuzhiyun * Clearing bss area is not done in Xloader. 45*4882a593Smuzhiyun * BSS area lies in the DDR location which is not yet initialized 46*4882a593Smuzhiyun * bss is assumed to be uninitialized. 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun ldmia sp!, {r0-r12,pc} 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun/* 51*4882a593Smuzhiyun ************************************************************************* 52*4882a593Smuzhiyun * 53*4882a593Smuzhiyun * CPU_init_critical registers 54*4882a593Smuzhiyun * 55*4882a593Smuzhiyun * setup important registers 56*4882a593Smuzhiyun * setup memory timing 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun ************************************************************************* 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyuncpu_init_crit: 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * flush v4 I/D caches 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun mov r0, #0 65*4882a593Smuzhiyun mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 66*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * enable instruction cache 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 72*4882a593Smuzhiyun orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 73*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Go setup Memory and board specific bits prior to relocation. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun stmdb sp!, {lr} 79*4882a593Smuzhiyun bl _main /* _main will call board_init_f */ 80*4882a593Smuzhiyun ldmia sp!, {pc} 81