1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/hardware.h>
11*4882a593Smuzhiyun #include <asm/arch/spr_misc.h>
12*4882a593Smuzhiyun
arch_cpu_init(void)13*4882a593Smuzhiyun int arch_cpu_init(void)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun struct misc_regs *const misc_p =
16*4882a593Smuzhiyun (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
17*4882a593Smuzhiyun u32 periph1_clken, periph_clk_cfg;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun periph1_clken = readl(&misc_p->periph1_clken);
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #if defined(CONFIG_SPEAR3XX)
22*4882a593Smuzhiyun periph1_clken |= MISC_GPT2ENB;
23*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR600)
24*4882a593Smuzhiyun periph1_clken |= MISC_GPT3ENB;
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #if defined(CONFIG_PL011_SERIAL)
28*4882a593Smuzhiyun periph1_clken |= MISC_UART0ENB;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun periph_clk_cfg = readl(&misc_p->periph_clk_cfg);
31*4882a593Smuzhiyun periph_clk_cfg &= ~CONFIG_SPEAR_UARTCLKMSK;
32*4882a593Smuzhiyun periph_clk_cfg |= CONFIG_SPEAR_UART48M;
33*4882a593Smuzhiyun writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun #if defined(CONFIG_ETH_DESIGNWARE)
36*4882a593Smuzhiyun periph1_clken |= MISC_ETHENB;
37*4882a593Smuzhiyun #endif
38*4882a593Smuzhiyun #if defined(CONFIG_DW_UDC)
39*4882a593Smuzhiyun periph1_clken |= MISC_USBDENB;
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun #if defined(CONFIG_SYS_I2C_DW)
42*4882a593Smuzhiyun periph1_clken |= MISC_I2CENB;
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun #if defined(CONFIG_ST_SMI)
45*4882a593Smuzhiyun periph1_clken |= MISC_SMIENB;
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun #if defined(CONFIG_NAND_FSMC)
48*4882a593Smuzhiyun periph1_clken |= MISC_FSMCENB;
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun #if defined(CONFIG_USB_EHCI_SPEAR)
51*4882a593Smuzhiyun periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun writel(periph1_clken, &misc_p->periph1_clken);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
enable_caches(void)59*4882a593Smuzhiyun void enable_caches(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun #ifndef CONFIG_SYS_ICACHE_OFF
62*4882a593Smuzhiyun icache_enable();
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
65*4882a593Smuzhiyun dcache_enable();
66*4882a593Smuzhiyun #endif
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #ifdef CONFIG_DISPLAY_CPUINFO
print_cpuinfo(void)70*4882a593Smuzhiyun int print_cpuinfo(void)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun #ifdef CONFIG_SPEAR300
73*4882a593Smuzhiyun printf("CPU: SPEAr300\n");
74*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR310)
75*4882a593Smuzhiyun printf("CPU: SPEAr310\n");
76*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR320)
77*4882a593Smuzhiyun printf("CPU: SPEAr320\n");
78*4882a593Smuzhiyun #elif defined(CONFIG_SPEAR600)
79*4882a593Smuzhiyun printf("CPU: SPEAr600\n");
80*4882a593Smuzhiyun #else
81*4882a593Smuzhiyun #error CPU not supported in spear platform
82*4882a593Smuzhiyun #endif
83*4882a593Smuzhiyun return 0;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC)
do_switch_ecc(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])88*4882a593Smuzhiyun static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
89*4882a593Smuzhiyun char *const argv[])
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun if (argc != 2)
92*4882a593Smuzhiyun goto usage;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (strncmp(argv[1], "hw", 2) == 0) {
95*4882a593Smuzhiyun /* 1-bit HW ECC */
96*4882a593Smuzhiyun printf("Switching to 1-bit HW ECC\n");
97*4882a593Smuzhiyun fsmc_nand_switch_ecc(1);
98*4882a593Smuzhiyun } else if (strncmp(argv[1], "bch4", 2) == 0) {
99*4882a593Smuzhiyun /* 4-bit SW ECC BCH4 */
100*4882a593Smuzhiyun printf("Switching to 4-bit SW ECC (BCH4)\n");
101*4882a593Smuzhiyun fsmc_nand_switch_ecc(4);
102*4882a593Smuzhiyun } else {
103*4882a593Smuzhiyun goto usage;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun usage:
109*4882a593Smuzhiyun printf("Usage: nandecc %s\n", cmdtp->usage);
110*4882a593Smuzhiyun return 1;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun U_BOOT_CMD(
114*4882a593Smuzhiyun nandecc, 2, 0, do_switch_ecc,
115*4882a593Smuzhiyun "switch NAND ECC calculation algorithm",
116*4882a593Smuzhiyun "hw|bch4 - Switch between NAND hardware 1-bit HW and"
117*4882a593Smuzhiyun " 4-bit SW BCH\n"
118*4882a593Smuzhiyun );
119*4882a593Smuzhiyun #endif
120