1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
3*4882a593Smuzhiyun * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4*4882a593Smuzhiyun * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5*4882a593Smuzhiyun * <armlinux@phytec.de>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <linux/errno.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <asm/arch/clock.h>
14*4882a593Smuzhiyun #include <asm/arch/iomux.h>
15*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #if defined(CONFIG_MX23)
18*4882a593Smuzhiyun #define DRIVE_OFFSET 0x200
19*4882a593Smuzhiyun #define PULL_OFFSET 0x400
20*4882a593Smuzhiyun #elif defined(CONFIG_MX28)
21*4882a593Smuzhiyun #define DRIVE_OFFSET 0x300
22*4882a593Smuzhiyun #define PULL_OFFSET 0x600
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun #error "Please select CONFIG_MX23 or CONFIG_MX28"
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /*
28*4882a593Smuzhiyun * configures a single pad in the iomuxer
29*4882a593Smuzhiyun */
mxs_iomux_setup_pad(iomux_cfg_t pad)30*4882a593Smuzhiyun int mxs_iomux_setup_pad(iomux_cfg_t pad)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun u32 reg, ofs, bp, bm;
33*4882a593Smuzhiyun void *iomux_base = (void *)MXS_PINCTRL_BASE;
34*4882a593Smuzhiyun struct mxs_register_32 *mxs_reg;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* muxsel */
37*4882a593Smuzhiyun ofs = 0x100;
38*4882a593Smuzhiyun ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
39*4882a593Smuzhiyun bp = PAD_PIN(pad) % 16 * 2;
40*4882a593Smuzhiyun bm = 0x3 << bp;
41*4882a593Smuzhiyun reg = readl(iomux_base + ofs);
42*4882a593Smuzhiyun reg &= ~bm;
43*4882a593Smuzhiyun reg |= PAD_MUXSEL(pad) << bp;
44*4882a593Smuzhiyun writel(reg, iomux_base + ofs);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* drive */
47*4882a593Smuzhiyun ofs = DRIVE_OFFSET;
48*4882a593Smuzhiyun ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
49*4882a593Smuzhiyun /* mA */
50*4882a593Smuzhiyun if (PAD_MA_VALID(pad)) {
51*4882a593Smuzhiyun bp = PAD_PIN(pad) % 8 * 4;
52*4882a593Smuzhiyun bm = 0x3 << bp;
53*4882a593Smuzhiyun reg = readl(iomux_base + ofs);
54*4882a593Smuzhiyun reg &= ~bm;
55*4882a593Smuzhiyun reg |= PAD_MA(pad) << bp;
56*4882a593Smuzhiyun writel(reg, iomux_base + ofs);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun /* vol */
59*4882a593Smuzhiyun if (PAD_VOL_VALID(pad)) {
60*4882a593Smuzhiyun bp = PAD_PIN(pad) % 8 * 4 + 2;
61*4882a593Smuzhiyun mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
62*4882a593Smuzhiyun if (PAD_VOL(pad))
63*4882a593Smuzhiyun writel(1 << bp, &mxs_reg->reg_set);
64*4882a593Smuzhiyun else
65*4882a593Smuzhiyun writel(1 << bp, &mxs_reg->reg_clr);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* pull */
69*4882a593Smuzhiyun if (PAD_PULL_VALID(pad)) {
70*4882a593Smuzhiyun ofs = PULL_OFFSET;
71*4882a593Smuzhiyun ofs += PAD_BANK(pad) * 0x10;
72*4882a593Smuzhiyun bp = PAD_PIN(pad);
73*4882a593Smuzhiyun mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
74*4882a593Smuzhiyun if (PAD_PULL(pad))
75*4882a593Smuzhiyun writel(1 << bp, &mxs_reg->reg_set);
76*4882a593Smuzhiyun else
77*4882a593Smuzhiyun writel(1 << bp, &mxs_reg->reg_clr);
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
mxs_iomux_setup_multiple_pads(const iomux_cfg_t * pad_list,unsigned count)83*4882a593Smuzhiyun int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun const iomux_cfg_t *p = pad_list;
86*4882a593Smuzhiyun int i;
87*4882a593Smuzhiyun int ret;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun for (i = 0; i < count; i++) {
90*4882a593Smuzhiyun ret = mxs_iomux_setup_pad(*p);
91*4882a593Smuzhiyun if (ret)
92*4882a593Smuzhiyun return ret;
93*4882a593Smuzhiyun p++;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98