1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2002
3*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4*4882a593Smuzhiyun * Marius Groeger <mgroeger@sysgo.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * (C) Copyright 2002
7*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8*4882a593Smuzhiyun * Alex Zuepke <azu@sysgo.de>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * (C) Copyright 2002
11*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * (C) Copyright 2009
14*4882a593Smuzhiyun * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * (C) Copyright 2009 DENX Software Engineering
17*4882a593Smuzhiyun * Author: John Rigby <jrigby@gmail.com>
18*4882a593Smuzhiyun * Add support for MX25
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <common.h>
24*4882a593Smuzhiyun #include <asm/io.h>
25*4882a593Smuzhiyun #include <asm/arch/imx-regs.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* nothing really to do with interrupts, just starts up a counter. */
28*4882a593Smuzhiyun /* The 32KHz 32-bit timer overruns in 134217 seconds */
timer_init(void)29*4882a593Smuzhiyun int timer_init(void)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun int i;
32*4882a593Smuzhiyun struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
33*4882a593Smuzhiyun struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* setup GP Timer 1 */
36*4882a593Smuzhiyun writel(GPT_CTRL_SWR, &gpt->ctrl);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun for (i = 0; i < 100; i++)
41*4882a593Smuzhiyun writel(0, &gpt->ctrl); /* We have no udelay by now */
42*4882a593Smuzhiyun writel(0, &gpt->pre); /* prescaler = 1 */
43*4882a593Smuzhiyun /* Freerun Mode, 32KHz input */
44*4882a593Smuzhiyun writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
45*4882a593Smuzhiyun &gpt->ctrl);
46*4882a593Smuzhiyun writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50