1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * WORK Microwave work_92105 board low level init 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2014 DENX Software Engineering GmbH 5*4882a593Smuzhiyun * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Low level init is called from SPL to set up the clocks. 8*4882a593Smuzhiyun * On entry, the LPC3250 is in Direct Run mode with all clocks 9*4882a593Smuzhiyun * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is 10*4882a593Smuzhiyun * 104 MHz and PCLK is 13 MHz. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * This code must run from SRAM so that the clock changes do 13*4882a593Smuzhiyun * not prevent it from executing. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun.globl lowlevel_init 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunlowlevel_init: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Set ARM, HCLK, PCLK dividers for normal mode */ 23*4882a593Smuzhiyun ldr r0, =0x0000003D 24*4882a593Smuzhiyun ldr r1, =0x40004040 25*4882a593Smuzhiyun str r0, [r1] 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Start HCLK PLL for 208 MHz */ 28*4882a593Smuzhiyun ldr r0, =0x0001401E 29*4882a593Smuzhiyun ldr r1, =0x40004058 30*4882a593Smuzhiyun str r0, [r1] 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* wait for HCLK PLL to lock */ 33*4882a593Smuzhiyun1: 34*4882a593Smuzhiyun ldr r0, [r1] 35*4882a593Smuzhiyun ands r0, r0, #1 36*4882a593Smuzhiyun beq 1b 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* switch to normal mode */ 39*4882a593Smuzhiyun ldr r1, =0x40004044 40*4882a593Smuzhiyun ldr r0, [r1] 41*4882a593Smuzhiyun orr r0, #0x00000004 42*4882a593Smuzhiyun str r0, [r1] 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Return to U-Boot via saved link register */ 45*4882a593Smuzhiyun mov pc, lr 46