1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <netdev.h>
9*4882a593Smuzhiyun #include <asm/arch/cpu.h>
10*4882a593Smuzhiyun #include <asm/arch/clk.h>
11*4882a593Smuzhiyun #include <asm/arch/wdt.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16*4882a593Smuzhiyun static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
17*4882a593Smuzhiyun
reset_cpu(ulong addr)18*4882a593Smuzhiyun void reset_cpu(ulong addr)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /* Enable watchdog clock */
21*4882a593Smuzhiyun setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* To be compatible with the original U-Boot code:
24*4882a593Smuzhiyun * addr: - 0: perform hard reset.
25*4882a593Smuzhiyun * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
26*4882a593Smuzhiyun if (addr == 0) {
27*4882a593Smuzhiyun /* Reset pulse length is 13005 peripheral clock frames */
28*4882a593Smuzhiyun writel(13000, &wdt->pulse);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* Force WDOG_RESET2 and RESOUT_N signal active */
31*4882a593Smuzhiyun writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
32*4882a593Smuzhiyun | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
33*4882a593Smuzhiyun } else {
34*4882a593Smuzhiyun /* Force match output active */
35*4882a593Smuzhiyun writel(0x01, &wdt->emr);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Internal reset on match output (no pulse on "RESOUT_N") */
38*4882a593Smuzhiyun writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun while (1)
42*4882a593Smuzhiyun /* NOP */;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #if defined(CONFIG_ARCH_CPU_INIT)
arch_cpu_init(void)46*4882a593Smuzhiyun int arch_cpu_init(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * It might be necessary to flush data cache, if U-Boot is loaded
50*4882a593Smuzhiyun * from kickstart bootloader, e.g. from S1L loader
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun flush_dcache_all();
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun #else
57*4882a593Smuzhiyun #error "You have to select CONFIG_ARCH_CPU_INIT"
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)61*4882a593Smuzhiyun int print_cpuinfo(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun printf("CPU: NXP LPC32XX\n");
64*4882a593Smuzhiyun printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
65*4882a593Smuzhiyun printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
66*4882a593Smuzhiyun printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun #endif
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #ifdef CONFIG_LPC32XX_ETH
cpu_eth_init(bd_t * bis)73*4882a593Smuzhiyun int cpu_eth_init(bd_t *bis)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun lpc32xx_eth_initialize(bis);
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun #endif
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