1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5*4882a593Smuzhiyun * Contributor: Mahavir Jain <mjain@marvell.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <asm/arch/cpu.h>
12*4882a593Smuzhiyun #include <asm/arch/armada100.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
15*4882a593Smuzhiyun #define SET_MRVL_ID (1<<8)
16*4882a593Smuzhiyun #define L2C_RAM_SEL (1<<4)
17*4882a593Smuzhiyun
arch_cpu_init(void)18*4882a593Smuzhiyun int arch_cpu_init(void)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun u32 val;
21*4882a593Smuzhiyun struct armd1cpu_registers *cpuregs =
22*4882a593Smuzhiyun (struct armd1cpu_registers *) ARMD1_CPU_BASE;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct armd1apb1_registers *apb1clkres =
25*4882a593Smuzhiyun (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct armd1mpmu_registers *mpmu =
28*4882a593Smuzhiyun (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
31*4882a593Smuzhiyun val = readl(&cpuregs->cpu_conf);
32*4882a593Smuzhiyun val = val | SET_MRVL_ID;
33*4882a593Smuzhiyun writel(val, &cpuregs->cpu_conf);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Enable Clocks for all hardware units */
36*4882a593Smuzhiyun writel(0xFFFFFFFF, &mpmu->acgr);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Turn on AIB and AIB-APB Functional clock */
39*4882a593Smuzhiyun writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* ensure L2 cache is not mapped as SRAM */
42*4882a593Smuzhiyun val = readl(&cpuregs->cpu_conf);
43*4882a593Smuzhiyun val = val & ~(L2C_RAM_SEL);
44*4882a593Smuzhiyun writel(val, &cpuregs->cpu_conf);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Enable GPIO clock */
47*4882a593Smuzhiyun writel(APBC_APBCLK, &apb1clkres->gpio);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #ifdef CONFIG_I2C_MV
50*4882a593Smuzhiyun /* Enable general I2C clock */
51*4882a593Smuzhiyun writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
52*4882a593Smuzhiyun writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Enable power I2C clock */
55*4882a593Smuzhiyun writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
56*4882a593Smuzhiyun writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * Enable Functional and APB clock at 14.7456MHz
61*4882a593Smuzhiyun * for configured UART console
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun #if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
64*4882a593Smuzhiyun writel(UARTCLK14745KHZ, &apb1clkres->uart3);
65*4882a593Smuzhiyun #elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
66*4882a593Smuzhiyun writel(UARTCLK14745KHZ, &apb1clkres->uart2);
67*4882a593Smuzhiyun #else
68*4882a593Smuzhiyun writel(UARTCLK14745KHZ, &apb1clkres->uart1);
69*4882a593Smuzhiyun #endif
70*4882a593Smuzhiyun icache_enable();
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun return 0;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)76*4882a593Smuzhiyun int print_cpuinfo(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun u32 id;
79*4882a593Smuzhiyun struct armd1cpu_registers *cpuregs =
80*4882a593Smuzhiyun (struct armd1cpu_registers *) ARMD1_CPU_BASE;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun id = readl(&cpuregs->chip_id);
83*4882a593Smuzhiyun printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
84*4882a593Smuzhiyun return 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #ifdef CONFIG_I2C_MV
i2c_clk_enable(void)89*4882a593Smuzhiyun void i2c_clk_enable(void)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun #endif
93