1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (c) 2004 Sascha Hauer <sascha@saschahauer.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #if defined (CONFIG_IMX) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 15*4882a593Smuzhiyun /* NOTE: This describes the proper use of this file. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. 18*4882a593Smuzhiyun * SH FIXME: 16780000 in our case 19*4882a593Smuzhiyun * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of 20*4882a593Smuzhiyun * the specified bus in HZ. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 23*4882a593Smuzhiyun get_systemPLLCLK(void)24*4882a593Smuzhiyunulong get_systemPLLCLK(void) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun /* FIXME: We assume System_SEL = 0 here */ 27*4882a593Smuzhiyun u32 spctl0 = SPCTL0; 28*4882a593Smuzhiyun u32 mfi = (spctl0 >> 10) & 0xf; 29*4882a593Smuzhiyun u32 mfn = spctl0 & 0x3f; 30*4882a593Smuzhiyun u32 mfd = (spctl0 >> 16) & 0x3f; 31*4882a593Smuzhiyun u32 pd = (spctl0 >> 26) & 0xf; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun mfi = mfi<=5 ? 5 : mfi; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun get_mcuPLLCLK(void)38*4882a593Smuzhiyunulong get_mcuPLLCLK(void) 39*4882a593Smuzhiyun { 40*4882a593Smuzhiyun /* FIXME: We assume System_SEL = 0 here */ 41*4882a593Smuzhiyun u32 mpctl0 = MPCTL0; 42*4882a593Smuzhiyun u32 mfi = (mpctl0 >> 10) & 0xf; 43*4882a593Smuzhiyun u32 mfn = mpctl0 & 0x3f; 44*4882a593Smuzhiyun u32 mfd = (mpctl0 >> 16) & 0x3f; 45*4882a593Smuzhiyun u32 pd = (mpctl0 >> 26) & 0xf; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun mfi = mfi<=5 ? 5 : mfi; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1); 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun get_FCLK(void)52*4882a593Smuzhiyunulong get_FCLK(void) 53*4882a593Smuzhiyun { 54*4882a593Smuzhiyun return (( CSCR>>15)&1) ? get_mcuPLLCLK()>>1 : get_mcuPLLCLK(); 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* return HCLK frequency */ get_HCLK(void)58*4882a593Smuzhiyunulong get_HCLK(void) 59*4882a593Smuzhiyun { 60*4882a593Smuzhiyun u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1; 61*4882a593Smuzhiyun printf("bclkdiv: %d\n", bclkdiv); 62*4882a593Smuzhiyun return get_systemPLLCLK() / bclkdiv; 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* return BCLK frequency */ get_BCLK(void)66*4882a593Smuzhiyunulong get_BCLK(void) 67*4882a593Smuzhiyun { 68*4882a593Smuzhiyun return get_HCLK(); 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun get_PERCLK1(void)71*4882a593Smuzhiyunulong get_PERCLK1(void) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun return get_systemPLLCLK() / (((PCDR) & 0xf)+1); 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun get_PERCLK2(void)76*4882a593Smuzhiyunulong get_PERCLK2(void) 77*4882a593Smuzhiyun { 78*4882a593Smuzhiyun return get_systemPLLCLK() / (((PCDR>>4) & 0xf)+1); 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun get_PERCLK3(void)81*4882a593Smuzhiyunulong get_PERCLK3(void) 82*4882a593Smuzhiyun { 83*4882a593Smuzhiyun return get_systemPLLCLK() / (((PCDR>>16) & 0x7f)+1); 84*4882a593Smuzhiyun } 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* defined (CONFIG_IMX) */ 87