1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Cirrus Logic EP93xx CPU-specific support. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2004, 2005 7*4882a593Smuzhiyun * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <common.h> 13*4882a593Smuzhiyun #include <asm/arch/ep93xx.h> 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */ reset_cpu(ulong addr)17*4882a593Smuzhiyunextern void reset_cpu(ulong addr) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; 20*4882a593Smuzhiyun uint32_t value; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Unlock DeviceCfg and set SWRST */ 23*4882a593Smuzhiyun writel(0xAA, &syscon->sysswlock); 24*4882a593Smuzhiyun value = readl(&syscon->devicecfg); 25*4882a593Smuzhiyun value |= SYSCON_DEVICECFG_SWRST; 26*4882a593Smuzhiyun writel(value, &syscon->devicecfg); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Unlock DeviceCfg and clear SWRST */ 29*4882a593Smuzhiyun writel(0xAA, &syscon->sysswlock); 30*4882a593Smuzhiyun value = readl(&syscon->devicecfg); 31*4882a593Smuzhiyun value &= ~SYSCON_DEVICECFG_SWRST; 32*4882a593Smuzhiyun writel(value, &syscon->devicecfg); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Dying... */ 35*4882a593Smuzhiyun while (1) 36*4882a593Smuzhiyun ; /* noop */ 37*4882a593Smuzhiyun } 38