1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * armboot - Startup Code for ARM1176 CPU-core 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2007 Samsung Electronics 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2008 7*4882a593Smuzhiyun * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 12*4882a593Smuzhiyun * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 13*4882a593Smuzhiyun * jsgood (jsgood.yang@samsung.com) 14*4882a593Smuzhiyun * Base codes by scsuh (sc.suh) 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun#include <asm-offsets.h> 18*4882a593Smuzhiyun#include <config.h> 19*4882a593Smuzhiyun#include <linux/linkage.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun#ifndef CONFIG_SYS_PHY_UBOOT_BASE 22*4882a593Smuzhiyun#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 23*4882a593Smuzhiyun#endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun/* 26*4882a593Smuzhiyun ************************************************************************* 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * Startup Code (reset vector) 29*4882a593Smuzhiyun * 30*4882a593Smuzhiyun * do important init only if we don't start from memory! 31*4882a593Smuzhiyun * setup Memory and board specific bits prior to relocation. 32*4882a593Smuzhiyun * relocate armboot to ram 33*4882a593Smuzhiyun * setup stack 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun ************************************************************************* 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun .globl reset 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunreset: 41*4882a593Smuzhiyun /* Allow the board to save important registers */ 42*4882a593Smuzhiyun b save_boot_params 43*4882a593Smuzhiyun.globl save_boot_params_ret 44*4882a593Smuzhiyunsave_boot_params_ret: 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * set the cpu to SVC32 mode 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun mrs r0, cpsr 50*4882a593Smuzhiyun bic r0, r0, #0x3f 51*4882a593Smuzhiyun orr r0, r0, #0xd3 52*4882a593Smuzhiyun msr cpsr, r0 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun/* 55*4882a593Smuzhiyun ************************************************************************* 56*4882a593Smuzhiyun * 57*4882a593Smuzhiyun * CPU_init_critical registers 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * setup important registers 60*4882a593Smuzhiyun * setup memory timing 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun ************************************************************************* 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * we do sys-critical inits only at reboot, 66*4882a593Smuzhiyun * not when booting from ram! 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyuncpu_init_crit: 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * When booting from NAND - it has definitely been a reset, so, no need 71*4882a593Smuzhiyun * to flush caches and disable the MMU 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun#ifndef CONFIG_SPL_BUILD 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * flush v4 I/D caches 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun mov r0, #0 78*4882a593Smuzhiyun mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 79*4882a593Smuzhiyun mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * disable MMU stuff and caches 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 85*4882a593Smuzhiyun bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 86*4882a593Smuzhiyun bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 87*4882a593Smuzhiyun orr r0, r0, #0x00000002 @ set bit 1 (A) Align 88*4882a593Smuzhiyun orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Prepare to disable the MMU */ 91*4882a593Smuzhiyun adr r2, mmu_disable_phys 92*4882a593Smuzhiyun sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 93*4882a593Smuzhiyun b mmu_disable 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun .align 5 96*4882a593Smuzhiyun /* Run in a single cache-line */ 97*4882a593Smuzhiyunmmu_disable: 98*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 99*4882a593Smuzhiyun nop 100*4882a593Smuzhiyun nop 101*4882a593Smuzhiyun mov pc, r2 102*4882a593Smuzhiyunmmu_disable_phys: 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun#endif 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Go setup Memory and board specific bits prior to relocation. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun bl lowlevel_init /* go setup pll,mux,memory */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun bl _main 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun/*------------------------------------------------------------------------------*/ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun .globl c_runtime_cpu_setup 116*4882a593Smuzhiyunc_runtime_cpu_setup: 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun mov pc, lr 119*4882a593Smuzhiyun 120*4882a593SmuzhiyunWEAK(save_boot_params) 121*4882a593Smuzhiyun b save_boot_params_ret /* back to my caller */ 122*4882a593SmuzhiyunENDPROC(save_boot_params) 123