1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 12*4882a593Smuzhiyun #include <asm/arch/clock.h> 13*4882a593Smuzhiyun mx31_uart1_hw_init(void)14*4882a593Smuzhiyunvoid mx31_uart1_hw_init(void) 15*4882a593Smuzhiyun { 16*4882a593Smuzhiyun /* setup pins for UART1 */ 17*4882a593Smuzhiyun mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); 18*4882a593Smuzhiyun mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); 19*4882a593Smuzhiyun mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); 20*4882a593Smuzhiyun mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun mx31_uart2_hw_init(void)23*4882a593Smuzhiyunvoid mx31_uart2_hw_init(void) 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun /* setup pins for UART2 */ 26*4882a593Smuzhiyun mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX); 27*4882a593Smuzhiyun mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX); 28*4882a593Smuzhiyun mx31_gpio_mux(MUX_RTS2__UART2_RTS_B); 29*4882a593Smuzhiyun mx31_gpio_mux(MUX_CTS2__UART2_CTS_B); 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifdef CONFIG_MXC_SPI 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Note: putting several spi setups here makes no sense as they may differ 35*4882a593Smuzhiyun * at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3) 36*4882a593Smuzhiyun */ mx31_spi2_hw_init(void)37*4882a593Smuzhiyunvoid mx31_spi2_hw_init(void) 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun /* SPI2 */ 40*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); 41*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); 42*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); 43*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); 44*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); 45*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); 46*4882a593Smuzhiyun mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* start SPI2 clock */ 49*4882a593Smuzhiyun __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); 50*4882a593Smuzhiyun } 51*4882a593Smuzhiyun #endif 52