1 /*
2 * (C) Copyright 2004 Texas Insturments
3 *
4 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * (C) Copyright 2002
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
10 *
11 * SPDX-License-Identifier: GPL-2.0+
12 */
13
14 /*
15 * CPU specific code
16 */
17
18 #include <common.h>
19 #include <command.h>
20 #include <asm/system.h>
21
22 static void cache_flush(void);
23
cleanup_before_linux(void)24 int cleanup_before_linux (void)
25 {
26 /*
27 * this function is called just before we call linux
28 * it prepares the processor for linux
29 *
30 * we turn off caches etc ...
31 */
32
33 disable_interrupts ();
34
35 /* turn off I/D-cache */
36 icache_disable();
37 dcache_disable();
38 /* flush I/D-cache */
39 cache_flush();
40
41 return 0;
42 }
43
cache_flush(void)44 static void cache_flush(void)
45 {
46 unsigned long i = 0;
47 /* clean entire data cache */
48 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
49 /* invalidate both caches and flush btb */
50 asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
51 /* mem barrier to sync things */
52 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
53 }
54
55 #ifndef CONFIG_SYS_DCACHE_OFF
invalidate_dcache_all(void)56 void invalidate_dcache_all(void)
57 {
58 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
59 }
60
flush_dcache_all(void)61 void flush_dcache_all(void)
62 {
63 asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
64 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
65 }
66
invalidate_dcache_range(unsigned long start,unsigned long stop)67 void invalidate_dcache_range(unsigned long start, unsigned long stop)
68 {
69 if (!check_cache_range(start, stop))
70 return;
71
72 while (start < stop) {
73 asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
74 start += CONFIG_SYS_CACHELINE_SIZE;
75 }
76 }
77
flush_dcache_range(unsigned long start,unsigned long stop)78 void flush_dcache_range(unsigned long start, unsigned long stop)
79 {
80 if (!check_cache_range(start, stop))
81 return;
82
83 while (start < stop) {
84 asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
85 start += CONFIG_SYS_CACHELINE_SIZE;
86 }
87
88 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
89 }
90
91 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
invalidate_dcache_all(void)92 void invalidate_dcache_all(void)
93 {
94 }
95
flush_dcache_all(void)96 void flush_dcache_all(void)
97 {
98 }
99 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
100
101 #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
enable_caches(void)102 void enable_caches(void)
103 {
104 #ifndef CONFIG_SYS_ICACHE_OFF
105 icache_enable();
106 #endif
107 #ifndef CONFIG_SYS_DCACHE_OFF
108 dcache_enable();
109 #endif
110 }
111 #endif
112