1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2004 Texas Insturments
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2002
5*4882a593Smuzhiyun * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6*4882a593Smuzhiyun * Marius Groeger <mgroeger@sysgo.de>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * (C) Copyright 2002
9*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /*
15*4882a593Smuzhiyun * CPU specific code
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <common.h>
19*4882a593Smuzhiyun #include <command.h>
20*4882a593Smuzhiyun #include <asm/system.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun static void cache_flush(void);
23*4882a593Smuzhiyun
cleanup_before_linux(void)24*4882a593Smuzhiyun int cleanup_before_linux (void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * this function is called just before we call linux
28*4882a593Smuzhiyun * it prepares the processor for linux
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * we turn off caches etc ...
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun disable_interrupts ();
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* turn off I/D-cache */
36*4882a593Smuzhiyun icache_disable();
37*4882a593Smuzhiyun dcache_disable();
38*4882a593Smuzhiyun /* flush I/D-cache */
39*4882a593Smuzhiyun cache_flush();
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
cache_flush(void)44*4882a593Smuzhiyun static void cache_flush(void)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun unsigned long i = 0;
47*4882a593Smuzhiyun /* clean entire data cache */
48*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i));
49*4882a593Smuzhiyun /* invalidate both caches and flush btb */
50*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i));
51*4882a593Smuzhiyun /* mem barrier to sync things */
52*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
invalidate_dcache_all(void)56*4882a593Smuzhiyun void invalidate_dcache_all(void)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
flush_dcache_all(void)61*4882a593Smuzhiyun void flush_dcache_all(void)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (0));
64*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
invalidate_dcache_range(unsigned long start,unsigned long stop)67*4882a593Smuzhiyun void invalidate_dcache_range(unsigned long start, unsigned long stop)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun if (!check_cache_range(start, stop))
70*4882a593Smuzhiyun return;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun while (start < stop) {
73*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (start));
74*4882a593Smuzhiyun start += CONFIG_SYS_CACHELINE_SIZE;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
flush_dcache_range(unsigned long start,unsigned long stop)78*4882a593Smuzhiyun void flush_dcache_range(unsigned long start, unsigned long stop)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun if (!check_cache_range(start, stop))
81*4882a593Smuzhiyun return;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun while (start < stop) {
84*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r" (start));
85*4882a593Smuzhiyun start += CONFIG_SYS_CACHELINE_SIZE;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
invalidate_dcache_all(void)92*4882a593Smuzhiyun void invalidate_dcache_all(void)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
flush_dcache_all(void)96*4882a593Smuzhiyun void flush_dcache_all(void)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)
enable_caches(void)102*4882a593Smuzhiyun void enable_caches(void)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun #ifndef CONFIG_SYS_ICACHE_OFF
105*4882a593Smuzhiyun icache_enable();
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
108*4882a593Smuzhiyun dcache_enable();
109*4882a593Smuzhiyun #endif
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun #endif
112