1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/arcregs.h> 9*4882a593Smuzhiyun #include <asm/cache.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 12*4882a593Smuzhiyun arch_cpu_init(void)13*4882a593Smuzhiyunint arch_cpu_init(void) 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun timer_init(); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun gd->cpu_clk = CONFIG_SYS_CLK_FREQ; 18*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun cache_init(); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun return 0; 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun arch_early_init_r(void)25*4882a593Smuzhiyunint arch_early_init_r(void) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; 28*4882a593Smuzhiyun gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; 29*4882a593Smuzhiyun return 0; 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* This is a dummy function on arc */ dram_init(void)33*4882a593Smuzhiyunint dram_init(void) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun return 0; 36*4882a593Smuzhiyun } 37