1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __ASM_ARC_CACHE_H 8*4882a593Smuzhiyun #define __ASM_ARC_CACHE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <config.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * As of today we may handle any L1 cache line length right in software. 14*4882a593Smuzhiyun * For that essentially cache line length is a variable not constant. 15*4882a593Smuzhiyun * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length 16*4882a593Smuzhiyun * that may exist in either L1 or L2 (AKA SLC) caches on ARC. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define ARCH_DMA_MINALIGN 128 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #if defined(ARC_MMU_ABSENT) 21*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 0 22*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V2) 23*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 2 24*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V3) 25*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 3 26*4882a593Smuzhiyun #elif defined(CONFIG_ARC_MMU_V4) 27*4882a593Smuzhiyun #define CONFIG_ARC_MMU_VER 4 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun void cache_init(void); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __ASM_ARC_CACHE_H */ 37