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65<p>
66Previous: <a href="AVR-Opcodes.html#AVR-Opcodes" accesskey="p" rel="previous">AVR Opcodes</a>, Up: <a href="AVR_002dDependent.html#AVR_002dDependent" accesskey="u" rel="up">AVR-Dependent</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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69<a name="Pseudo-Instructions"></a>
70<h4 class="subsection">9.5.4 Pseudo Instructions</h4>
71
72<p>The only available pseudo-instruction <code>__gcc_isr</code> can be activated by
73option <samp>-mgcc-isr</samp>.
74</p>
75<dl compact="compact">
76<dt><code>__gcc_isr 1</code></dt>
77<dd><p>Emit code chunk to be used in avr-gcc ISR prologue.
78It will expand to at most six 1-word instructions, all optional:
79push of <code>tmp_reg</code>, push of <code>SREG</code>,
80push and clear of <code>zero_reg</code>, push of <var>Reg</var>.
81</p>
82</dd>
83<dt><code>__gcc_isr 2</code></dt>
84<dd><p>Emit code chunk to be used in an avr-gcc ISR epilogue.
85It will expand to at most five 1-word instructions, all optional:
86pop of <var>Reg</var>, pop of <code>zero_reg</code>,
87pop of <code>SREG</code>, pop of <code>tmp_reg</code>.
88</p>
89</dd>
90<dt><code>__gcc_isr 0, <var>Reg</var></code></dt>
91<dd><p>Finish avr-gcc ISR function.  Scan code since the last prologue
92for usage of: <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code>.
93Prologue chunk and epilogue chunks will be replaced by appropriate code
94to save / restore <code>SREG</code>, <code>tmp_reg</code>, <code>zero_reg</code> and <var>Reg</var>.
95</p>
96</dd>
97</dl>
98
99<p>Example input:
100</p>
101<div class="example">
102<pre class="example">__vector1:
103    __gcc_isr 1
104    lds r24, var
105    inc r24
106    sts var, r24
107    __gcc_isr 2
108    reti
109    __gcc_isr 0, r24
110</pre></div>
111
112<p>Example output:
113</p>
114<div class="example">
115<pre class="example">00000000 &lt;__vector1&gt;:
116   0:   8f 93           push    r24
117   2:   8f b7           in      r24, 0x3f
118   4:   8f 93           push    r24
119   6:   80 91 60 00     lds     r24, 0x0060     ; 0x800060 &lt;var&gt;
120   a:   83 95           inc     r24
121   c:   80 93 60 00     sts     0x0060, r24     ; 0x800060 &lt;var&gt;
122  10:   8f 91           pop     r24
123  12:   8f bf           out     0x3f, r24
124  14:   8f 91           pop     r24
125  16:   18 95           reti
126</pre></div>
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