xref: /OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/tm/tm-signal-context-chk-vsx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2016, Cyril Bur, IBM Corp.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Test the kernel's signal frame code.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * The kernel sets up two sets of ucontexts if the signal was to be
8*4882a593Smuzhiyun  * delivered while the thread was in a transaction (referred too as
9*4882a593Smuzhiyun  * first and second contexts).
10*4882a593Smuzhiyun  * Expected behaviour is that the checkpointed state is in the user
11*4882a593Smuzhiyun  * context passed to the signal handler (first context). The speculated
12*4882a593Smuzhiyun  * state can be accessed with the uc_link pointer (second context).
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * The rationale for this is that if TM unaware code (which linked
15*4882a593Smuzhiyun  * against TM libs) installs a signal handler it will not know of the
16*4882a593Smuzhiyun  * speculative nature of the 'live' registers and may infer the wrong
17*4882a593Smuzhiyun  * thing.
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <stdlib.h>
21*4882a593Smuzhiyun #include <stdio.h>
22*4882a593Smuzhiyun #include <string.h>
23*4882a593Smuzhiyun #include <signal.h>
24*4882a593Smuzhiyun #include <unistd.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <altivec.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "utils.h"
29*4882a593Smuzhiyun #include "tm.h"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define MAX_ATTEMPT 500000
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define NV_VSX_REGS 12 /* Number of VSX registers to check. */
34*4882a593Smuzhiyun #define VSX20 20 /* First VSX register to check in vsr20-vsr31 subset */
35*4882a593Smuzhiyun #define FPR20 20 /* FPR20 overlaps VSX20 most significant doubleword */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun long tm_signal_self_context_load(pid_t pid, long *gprs, double *fps, vector int *vms, vector int *vss);
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static sig_atomic_t fail, broken;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* Test only 12 vsx registers from vsr20 to vsr31 */
42*4882a593Smuzhiyun vector int vsxs[] = {
43*4882a593Smuzhiyun 	/* First context will be set with these values, i.e. non-speculative */
44*4882a593Smuzhiyun 	/* VSX20     ,  VSX21      , ... */
45*4882a593Smuzhiyun 	{ 1, 2, 3, 4},{ 5, 6, 7, 8},{ 9,10,11,12},
46*4882a593Smuzhiyun 	{13,14,15,16},{17,18,19,20},{21,22,23,24},
47*4882a593Smuzhiyun 	{25,26,27,28},{29,30,31,32},{33,34,35,36},
48*4882a593Smuzhiyun 	{37,38,39,40},{41,42,43,44},{45,46,47,48},
49*4882a593Smuzhiyun 	/* Second context will be set with these values, i.e. speculative */
50*4882a593Smuzhiyun 	/* VSX20         ,  VSX21          , ... */
51*4882a593Smuzhiyun 	{-1, -2, -3, -4 },{-5, -6, -7, -8 },{-9, -10,-11,-12},
52*4882a593Smuzhiyun 	{-13,-14,-15,-16},{-17,-18,-19,-20},{-21,-22,-23,-24},
53*4882a593Smuzhiyun 	{-25,-26,-27,-28},{-29,-30,-31,-32},{-33,-34,-35,-36},
54*4882a593Smuzhiyun 	{-37,-38,-39,-40},{-41,-42,-43,-44},{-45,-46,-47,-48}
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun 
signal_usr1(int signum,siginfo_t * info,void * uc)57*4882a593Smuzhiyun static void signal_usr1(int signum, siginfo_t *info, void *uc)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun 	int i, j;
60*4882a593Smuzhiyun 	uint8_t vsx[sizeof(vector int)];
61*4882a593Smuzhiyun 	uint8_t vsx_tm[sizeof(vector int)];
62*4882a593Smuzhiyun 	ucontext_t *ucp = uc;
63*4882a593Smuzhiyun 	ucontext_t *tm_ucp = ucp->uc_link;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/*
66*4882a593Smuzhiyun 	 * FP registers and VMX registers overlap the VSX registers.
67*4882a593Smuzhiyun 	 *
68*4882a593Smuzhiyun 	 * FP registers (f0-31) overlap the most significant 64 bits of VSX
69*4882a593Smuzhiyun 	 * registers vsr0-31, whilst VMX registers vr0-31, being 128-bit like
70*4882a593Smuzhiyun 	 * the VSX registers, overlap fully the other half of VSX registers,
71*4882a593Smuzhiyun 	 * i.e. vr0-31 overlaps fully vsr32-63.
72*4882a593Smuzhiyun 	 *
73*4882a593Smuzhiyun 	 * Due to compatibility and historical reasons (VMX/Altivec support
74*4882a593Smuzhiyun 	 * appeared first on the architecture), VMX registers vr0-31 (so VSX
75*4882a593Smuzhiyun 	 * half vsr32-63 too) are stored right after the v_regs pointer, in an
76*4882a593Smuzhiyun 	 * area allocated for 'vmx_reverse' array (please see
77*4882a593Smuzhiyun 	 * arch/powerpc/include/uapi/asm/sigcontext.h for details about the
78*4882a593Smuzhiyun 	 * mcontext_t structure on Power).
79*4882a593Smuzhiyun 	 *
80*4882a593Smuzhiyun 	 * The other VSX half (vsr0-31) is hence stored below vr0-31/vsr32-63
81*4882a593Smuzhiyun 	 * registers, but only the least significant 64 bits of vsr0-31. The
82*4882a593Smuzhiyun 	 * most significant 64 bits of vsr0-31 (f0-31), as it overlaps the FP
83*4882a593Smuzhiyun 	 * registers, is kept in fp_regs.
84*4882a593Smuzhiyun 	 *
85*4882a593Smuzhiyun 	 * v_regs is a 16 byte aligned pointer at the start of vmx_reserve
86*4882a593Smuzhiyun 	 * (vmx_reserve may or may not be 16 aligned) where the v_regs structure
87*4882a593Smuzhiyun 	 * exists, so v_regs points to where vr0-31 / vsr32-63 registers are
88*4882a593Smuzhiyun 	 * fully stored. Since v_regs type is elf_vrregset_t, v_regs + 1
89*4882a593Smuzhiyun 	 * skips all the slots used to store vr0-31 / vsr32-64 and points to
90*4882a593Smuzhiyun 	 * part of one VSX half, i.e. v_regs + 1 points to the least significant
91*4882a593Smuzhiyun 	 * 64 bits of vsr0-31. The other part of this half (the most significant
92*4882a593Smuzhiyun 	 * part of vsr0-31) is stored in fp_regs.
93*4882a593Smuzhiyun 	 *
94*4882a593Smuzhiyun 	 */
95*4882a593Smuzhiyun 	/* Get pointer to least significant doubleword of vsr0-31 */
96*4882a593Smuzhiyun 	long *vsx_ptr = (long *)(ucp->uc_mcontext.v_regs + 1);
97*4882a593Smuzhiyun 	long *tm_vsx_ptr = (long *)(tm_ucp->uc_mcontext.v_regs + 1);
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	/* Check first context. Print all mismatches. */
100*4882a593Smuzhiyun 	for (i = 0; i < NV_VSX_REGS; i++) {
101*4882a593Smuzhiyun 		/*
102*4882a593Smuzhiyun 		 * Copy VSX most significant doubleword from fp_regs and
103*4882a593Smuzhiyun 		 * copy VSX least significant one from 64-bit slots below
104*4882a593Smuzhiyun 		 * saved VMX registers.
105*4882a593Smuzhiyun 		 */
106*4882a593Smuzhiyun 		memcpy(vsx, &ucp->uc_mcontext.fp_regs[FPR20 + i], 8);
107*4882a593Smuzhiyun 		memcpy(vsx + 8, &vsx_ptr[VSX20 + i], 8);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 		fail = memcmp(vsx, &vsxs[i], sizeof(vector int));
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 		if (fail) {
112*4882a593Smuzhiyun 			broken = 1;
113*4882a593Smuzhiyun 			printf("VSX%d (1st context) == 0x", VSX20 + i);
114*4882a593Smuzhiyun 			for (j = 0; j < 16; j++)
115*4882a593Smuzhiyun 				printf("%02x", vsx[j]);
116*4882a593Smuzhiyun 			printf(" instead of 0x");
117*4882a593Smuzhiyun 			for (j = 0; j < 4; j++)
118*4882a593Smuzhiyun 				printf("%08x", vsxs[i][j]);
119*4882a593Smuzhiyun 			printf(" (expected)\n");
120*4882a593Smuzhiyun 		}
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* Check second context. Print all mismatches. */
124*4882a593Smuzhiyun 	for (i = 0; i < NV_VSX_REGS; i++) {
125*4882a593Smuzhiyun 		/*
126*4882a593Smuzhiyun 		 * Copy VSX most significant doubleword from fp_regs and
127*4882a593Smuzhiyun 		 * copy VSX least significant one from 64-bit slots below
128*4882a593Smuzhiyun 		 * saved VMX registers.
129*4882a593Smuzhiyun 		 */
130*4882a593Smuzhiyun 		memcpy(vsx_tm, &tm_ucp->uc_mcontext.fp_regs[FPR20 + i], 8);
131*4882a593Smuzhiyun 		memcpy(vsx_tm + 8, &tm_vsx_ptr[VSX20 + i], 8);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 		fail = memcmp(vsx_tm, &vsxs[NV_VSX_REGS + i], sizeof(vector int));
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 		if (fail) {
136*4882a593Smuzhiyun 			broken = 1;
137*4882a593Smuzhiyun 			printf("VSX%d (2nd context) == 0x", VSX20 + i);
138*4882a593Smuzhiyun 			for (j = 0; j < 16; j++)
139*4882a593Smuzhiyun 				printf("%02x", vsx_tm[j]);
140*4882a593Smuzhiyun 			printf(" instead of 0x");
141*4882a593Smuzhiyun 			for (j = 0; j < 4; j++)
142*4882a593Smuzhiyun 				printf("%08x", vsxs[NV_VSX_REGS + i][j]);
143*4882a593Smuzhiyun 			printf("(expected)\n");
144*4882a593Smuzhiyun 		}
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun 
tm_signal_context_chk()148*4882a593Smuzhiyun static int tm_signal_context_chk()
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun 	struct sigaction act;
151*4882a593Smuzhiyun 	int i;
152*4882a593Smuzhiyun 	long rc;
153*4882a593Smuzhiyun 	pid_t pid = getpid();
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	SKIP_IF(!have_htm());
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	act.sa_sigaction = signal_usr1;
158*4882a593Smuzhiyun 	sigemptyset(&act.sa_mask);
159*4882a593Smuzhiyun 	act.sa_flags = SA_SIGINFO;
160*4882a593Smuzhiyun 	if (sigaction(SIGUSR1, &act, NULL) < 0) {
161*4882a593Smuzhiyun 		perror("sigaction sigusr1");
162*4882a593Smuzhiyun 		exit(1);
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	i = 0;
166*4882a593Smuzhiyun 	while (i < MAX_ATTEMPT && !broken) {
167*4882a593Smuzhiyun                /*
168*4882a593Smuzhiyun                 * tm_signal_self_context_load will set both first and second
169*4882a593Smuzhiyun                 * contexts accordingly to the values passed through non-NULL
170*4882a593Smuzhiyun                 * array pointers to it, in that case 'vsxs', and invoke the
171*4882a593Smuzhiyun                 * signal handler installed for SIGUSR1.
172*4882a593Smuzhiyun                 */
173*4882a593Smuzhiyun 		rc = tm_signal_self_context_load(pid, NULL, NULL, NULL, vsxs);
174*4882a593Smuzhiyun 		FAIL_IF(rc != pid);
175*4882a593Smuzhiyun 		i++;
176*4882a593Smuzhiyun 	}
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	return (broken);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
main(void)181*4882a593Smuzhiyun int main(void)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun 	return test_harness(tm_signal_context_chk, "tm_signal_context_chk_vsx");
184*4882a593Smuzhiyun }
185