1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2009 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * provides masks and opcode images for use by code generation, emulation 6*4882a593Smuzhiyun * and for instructions that older assemblers might not know about 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _ASM_POWERPC_PPC_OPCODE_H 9*4882a593Smuzhiyun #define _ASM_POWERPC_PPC_OPCODE_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun # define stringify_in_c(...) __VA_ARGS__ 13*4882a593Smuzhiyun # define ASM_CONST(x) x 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define PPC_INST_VCMPEQUD_RC 0x100000c7 17*4882a593Smuzhiyun #define PPC_INST_VCMPEQUB_RC 0x10000006 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define __PPC_RC21 (0x1 << 10) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* macros to insert fields into opcodes */ 22*4882a593Smuzhiyun #define ___PPC_RA(a) (((a) & 0x1f) << 16) 23*4882a593Smuzhiyun #define ___PPC_RB(b) (((b) & 0x1f) << 11) 24*4882a593Smuzhiyun #define ___PPC_RS(s) (((s) & 0x1f) << 21) 25*4882a593Smuzhiyun #define ___PPC_RT(t) ___PPC_RS(t) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define VCMPEQUD_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUD_RC | \ 28*4882a593Smuzhiyun ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 29*4882a593Smuzhiyun ___PPC_RB(vrb) | __PPC_RC21) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define VCMPEQUB_RC(vrt, vra, vrb) stringify_in_c(.long PPC_INST_VCMPEQUB_RC | \ 32*4882a593Smuzhiyun ___PPC_RT(vrt) | ___PPC_RA(vra) | \ 33*4882a593Smuzhiyun ___PPC_RB(vrb) | __PPC_RC21) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif /* _ASM_POWERPC_PPC_OPCODE_H */ 36