1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2016, Cyril Bur, IBM Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _SELFTESTS_POWERPC_GPR_ASM_H 7*4882a593Smuzhiyun #define _SELFTESTS_POWERPC_GPR_ASM_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "basic_asm.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define __PUSH_NVREGS(top_pos); \ 12*4882a593Smuzhiyun std r31,(top_pos)(%r1); \ 13*4882a593Smuzhiyun std r30,(top_pos - 8)(%r1); \ 14*4882a593Smuzhiyun std r29,(top_pos - 16)(%r1); \ 15*4882a593Smuzhiyun std r28,(top_pos - 24)(%r1); \ 16*4882a593Smuzhiyun std r27,(top_pos - 32)(%r1); \ 17*4882a593Smuzhiyun std r26,(top_pos - 40)(%r1); \ 18*4882a593Smuzhiyun std r25,(top_pos - 48)(%r1); \ 19*4882a593Smuzhiyun std r24,(top_pos - 56)(%r1); \ 20*4882a593Smuzhiyun std r23,(top_pos - 64)(%r1); \ 21*4882a593Smuzhiyun std r22,(top_pos - 72)(%r1); \ 22*4882a593Smuzhiyun std r21,(top_pos - 80)(%r1); \ 23*4882a593Smuzhiyun std r20,(top_pos - 88)(%r1); \ 24*4882a593Smuzhiyun std r19,(top_pos - 96)(%r1); \ 25*4882a593Smuzhiyun std r18,(top_pos - 104)(%r1); \ 26*4882a593Smuzhiyun std r17,(top_pos - 112)(%r1); \ 27*4882a593Smuzhiyun std r16,(top_pos - 120)(%r1); \ 28*4882a593Smuzhiyun std r15,(top_pos - 128)(%r1); \ 29*4882a593Smuzhiyun std r14,(top_pos - 136)(%r1) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define __POP_NVREGS(top_pos); \ 32*4882a593Smuzhiyun ld r31,(top_pos)(%r1); \ 33*4882a593Smuzhiyun ld r30,(top_pos - 8)(%r1); \ 34*4882a593Smuzhiyun ld r29,(top_pos - 16)(%r1); \ 35*4882a593Smuzhiyun ld r28,(top_pos - 24)(%r1); \ 36*4882a593Smuzhiyun ld r27,(top_pos - 32)(%r1); \ 37*4882a593Smuzhiyun ld r26,(top_pos - 40)(%r1); \ 38*4882a593Smuzhiyun ld r25,(top_pos - 48)(%r1); \ 39*4882a593Smuzhiyun ld r24,(top_pos - 56)(%r1); \ 40*4882a593Smuzhiyun ld r23,(top_pos - 64)(%r1); \ 41*4882a593Smuzhiyun ld r22,(top_pos - 72)(%r1); \ 42*4882a593Smuzhiyun ld r21,(top_pos - 80)(%r1); \ 43*4882a593Smuzhiyun ld r20,(top_pos - 88)(%r1); \ 44*4882a593Smuzhiyun ld r19,(top_pos - 96)(%r1); \ 45*4882a593Smuzhiyun ld r18,(top_pos - 104)(%r1); \ 46*4882a593Smuzhiyun ld r17,(top_pos - 112)(%r1); \ 47*4882a593Smuzhiyun ld r16,(top_pos - 120)(%r1); \ 48*4882a593Smuzhiyun ld r15,(top_pos - 128)(%r1); \ 49*4882a593Smuzhiyun ld r14,(top_pos - 136)(%r1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PUSH_NVREGS(stack_size) \ 52*4882a593Smuzhiyun __PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 18 NV FPU REGS */ 55*4882a593Smuzhiyun #define PUSH_NVREGS_BELOW_FPU(stack_size) \ 56*4882a593Smuzhiyun __PUSH_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define POP_NVREGS(stack_size) \ 59*4882a593Smuzhiyun __POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 18 NV FPU REGS */ 62*4882a593Smuzhiyun #define POP_NVREGS_BELOW_FPU(stack_size) \ 63*4882a593Smuzhiyun __POP_NVREGS(stack_size + STACK_FRAME_MIN_SIZE - (18 * 8)) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * Careful calling this, it will 'clobber' NVGPRs (by design) 67*4882a593Smuzhiyun * Don't call this from C 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun FUNC_START(load_gpr) 70*4882a593Smuzhiyun ld r14,0(r3) 71*4882a593Smuzhiyun ld r15,8(r3) 72*4882a593Smuzhiyun ld r16,16(r3) 73*4882a593Smuzhiyun ld r17,24(r3) 74*4882a593Smuzhiyun ld r18,32(r3) 75*4882a593Smuzhiyun ld r19,40(r3) 76*4882a593Smuzhiyun ld r20,48(r3) 77*4882a593Smuzhiyun ld r21,56(r3) 78*4882a593Smuzhiyun ld r22,64(r3) 79*4882a593Smuzhiyun ld r23,72(r3) 80*4882a593Smuzhiyun ld r24,80(r3) 81*4882a593Smuzhiyun ld r25,88(r3) 82*4882a593Smuzhiyun ld r26,96(r3) 83*4882a593Smuzhiyun ld r27,104(r3) 84*4882a593Smuzhiyun ld r28,112(r3) 85*4882a593Smuzhiyun ld r29,120(r3) 86*4882a593Smuzhiyun ld r30,128(r3) 87*4882a593Smuzhiyun ld r31,136(r3) 88*4882a593Smuzhiyun blr 89*4882a593Smuzhiyun FUNC_END(load_gpr) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* _SELFTESTS_POWERPC_GPR_ASM_H */ 93