1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Test for s390x CPU resets
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020, IBM
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <stdio.h>
9*4882a593Smuzhiyun #include <stdlib.h>
10*4882a593Smuzhiyun #include <string.h>
11*4882a593Smuzhiyun #include <sys/ioctl.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "test_util.h"
14*4882a593Smuzhiyun #include "kvm_util.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define VCPU_ID 3
17*4882a593Smuzhiyun #define LOCAL_IRQS 32
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct kvm_s390_irq buf[VCPU_ID + LOCAL_IRQS];
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct kvm_vm *vm;
22*4882a593Smuzhiyun struct kvm_run *run;
23*4882a593Smuzhiyun struct kvm_sync_regs *sync_regs;
24*4882a593Smuzhiyun static uint8_t regs_null[512];
25*4882a593Smuzhiyun
guest_code_initial(void)26*4882a593Smuzhiyun static void guest_code_initial(void)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun /* set several CRs to "safe" value */
29*4882a593Smuzhiyun unsigned long cr2_59 = 0x10; /* enable guarded storage */
30*4882a593Smuzhiyun unsigned long cr8_63 = 0x1; /* monitor mask = 1 */
31*4882a593Smuzhiyun unsigned long cr10 = 1; /* PER START */
32*4882a593Smuzhiyun unsigned long cr11 = -1; /* PER END */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Dirty registers */
36*4882a593Smuzhiyun asm volatile (
37*4882a593Smuzhiyun " lghi 2,0x11\n" /* Round toward 0 */
38*4882a593Smuzhiyun " sfpc 2\n" /* set fpc to !=0 */
39*4882a593Smuzhiyun " lctlg 2,2,%0\n"
40*4882a593Smuzhiyun " lctlg 8,8,%1\n"
41*4882a593Smuzhiyun " lctlg 10,10,%2\n"
42*4882a593Smuzhiyun " lctlg 11,11,%3\n"
43*4882a593Smuzhiyun /* now clobber some general purpose regs */
44*4882a593Smuzhiyun " llihh 0,0xffff\n"
45*4882a593Smuzhiyun " llihl 1,0x5555\n"
46*4882a593Smuzhiyun " llilh 2,0xaaaa\n"
47*4882a593Smuzhiyun " llill 3,0x0000\n"
48*4882a593Smuzhiyun /* now clobber a floating point reg */
49*4882a593Smuzhiyun " lghi 4,0x1\n"
50*4882a593Smuzhiyun " cdgbr 0,4\n"
51*4882a593Smuzhiyun /* now clobber an access reg */
52*4882a593Smuzhiyun " sar 9,4\n"
53*4882a593Smuzhiyun /* We embed diag 501 here to control register content */
54*4882a593Smuzhiyun " diag 0,0,0x501\n"
55*4882a593Smuzhiyun :
56*4882a593Smuzhiyun : "m" (cr2_59), "m" (cr8_63), "m" (cr10), "m" (cr11)
57*4882a593Smuzhiyun /* no clobber list as this should not return */
58*4882a593Smuzhiyun );
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
test_one_reg(uint64_t id,uint64_t value)61*4882a593Smuzhiyun static void test_one_reg(uint64_t id, uint64_t value)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun struct kvm_one_reg reg;
64*4882a593Smuzhiyun uint64_t eval_reg;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun reg.addr = (uintptr_t)&eval_reg;
67*4882a593Smuzhiyun reg.id = id;
68*4882a593Smuzhiyun vcpu_get_reg(vm, VCPU_ID, ®);
69*4882a593Smuzhiyun TEST_ASSERT(eval_reg == value, "value == 0x%lx", value);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
assert_noirq(void)72*4882a593Smuzhiyun static void assert_noirq(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct kvm_s390_irq_state irq_state;
75*4882a593Smuzhiyun int irqs;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun irq_state.len = sizeof(buf);
78*4882a593Smuzhiyun irq_state.buf = (unsigned long)buf;
79*4882a593Smuzhiyun irqs = _vcpu_ioctl(vm, VCPU_ID, KVM_S390_GET_IRQ_STATE, &irq_state);
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * irqs contains the number of retrieved interrupts. Any interrupt
82*4882a593Smuzhiyun * (notably, the emergency call interrupt we have injected) should
83*4882a593Smuzhiyun * be cleared by the resets, so this should be 0.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun TEST_ASSERT(irqs >= 0, "Could not fetch IRQs: errno %d\n", errno);
86*4882a593Smuzhiyun TEST_ASSERT(!irqs, "IRQ pending");
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
assert_clear(void)89*4882a593Smuzhiyun static void assert_clear(void)
90*4882a593Smuzhiyun {
91*4882a593Smuzhiyun struct kvm_sregs sregs;
92*4882a593Smuzhiyun struct kvm_regs regs;
93*4882a593Smuzhiyun struct kvm_fpu fpu;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun vcpu_regs_get(vm, VCPU_ID, ®s);
96*4882a593Smuzhiyun TEST_ASSERT(!memcmp(®s.gprs, regs_null, sizeof(regs.gprs)), "grs == 0");
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun vcpu_sregs_get(vm, VCPU_ID, &sregs);
99*4882a593Smuzhiyun TEST_ASSERT(!memcmp(&sregs.acrs, regs_null, sizeof(sregs.acrs)), "acrs == 0");
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun vcpu_fpu_get(vm, VCPU_ID, &fpu);
102*4882a593Smuzhiyun TEST_ASSERT(!memcmp(&fpu.fprs, regs_null, sizeof(fpu.fprs)), "fprs == 0");
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* sync regs */
105*4882a593Smuzhiyun TEST_ASSERT(!memcmp(sync_regs->gprs, regs_null, sizeof(sync_regs->gprs)),
106*4882a593Smuzhiyun "gprs0-15 == 0 (sync_regs)");
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun TEST_ASSERT(!memcmp(sync_regs->acrs, regs_null, sizeof(sync_regs->acrs)),
109*4882a593Smuzhiyun "acrs0-15 == 0 (sync_regs)");
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun TEST_ASSERT(!memcmp(sync_regs->vrs, regs_null, sizeof(sync_regs->vrs)),
112*4882a593Smuzhiyun "vrs0-15 == 0 (sync_regs)");
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
assert_initial_noclear(void)115*4882a593Smuzhiyun static void assert_initial_noclear(void)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun TEST_ASSERT(sync_regs->gprs[0] == 0xffff000000000000UL,
118*4882a593Smuzhiyun "gpr0 == 0xffff000000000000 (sync_regs)");
119*4882a593Smuzhiyun TEST_ASSERT(sync_regs->gprs[1] == 0x0000555500000000UL,
120*4882a593Smuzhiyun "gpr1 == 0x0000555500000000 (sync_regs)");
121*4882a593Smuzhiyun TEST_ASSERT(sync_regs->gprs[2] == 0x00000000aaaa0000UL,
122*4882a593Smuzhiyun "gpr2 == 0x00000000aaaa0000 (sync_regs)");
123*4882a593Smuzhiyun TEST_ASSERT(sync_regs->gprs[3] == 0x0000000000000000UL,
124*4882a593Smuzhiyun "gpr3 == 0x0000000000000000 (sync_regs)");
125*4882a593Smuzhiyun TEST_ASSERT(sync_regs->fprs[0] == 0x3ff0000000000000UL,
126*4882a593Smuzhiyun "fpr0 == 0f1 (sync_regs)");
127*4882a593Smuzhiyun TEST_ASSERT(sync_regs->acrs[9] == 1, "ar9 == 1 (sync_regs)");
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
assert_initial(void)130*4882a593Smuzhiyun static void assert_initial(void)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct kvm_sregs sregs;
133*4882a593Smuzhiyun struct kvm_fpu fpu;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /* KVM_GET_SREGS */
136*4882a593Smuzhiyun vcpu_sregs_get(vm, VCPU_ID, &sregs);
137*4882a593Smuzhiyun TEST_ASSERT(sregs.crs[0] == 0xE0UL, "cr0 == 0xE0 (KVM_GET_SREGS)");
138*4882a593Smuzhiyun TEST_ASSERT(sregs.crs[14] == 0xC2000000UL,
139*4882a593Smuzhiyun "cr14 == 0xC2000000 (KVM_GET_SREGS)");
140*4882a593Smuzhiyun TEST_ASSERT(!memcmp(&sregs.crs[1], regs_null, sizeof(sregs.crs[1]) * 12),
141*4882a593Smuzhiyun "cr1-13 == 0 (KVM_GET_SREGS)");
142*4882a593Smuzhiyun TEST_ASSERT(sregs.crs[15] == 0, "cr15 == 0 (KVM_GET_SREGS)");
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* sync regs */
145*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[0] == 0xE0UL, "cr0 == 0xE0 (sync_regs)");
146*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[14] == 0xC2000000UL,
147*4882a593Smuzhiyun "cr14 == 0xC2000000 (sync_regs)");
148*4882a593Smuzhiyun TEST_ASSERT(!memcmp(&sync_regs->crs[1], regs_null, 8 * 12),
149*4882a593Smuzhiyun "cr1-13 == 0 (sync_regs)");
150*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[15] == 0, "cr15 == 0 (sync_regs)");
151*4882a593Smuzhiyun TEST_ASSERT(sync_regs->fpc == 0, "fpc == 0 (sync_regs)");
152*4882a593Smuzhiyun TEST_ASSERT(sync_regs->todpr == 0, "todpr == 0 (sync_regs)");
153*4882a593Smuzhiyun TEST_ASSERT(sync_regs->cputm == 0, "cputm == 0 (sync_regs)");
154*4882a593Smuzhiyun TEST_ASSERT(sync_regs->ckc == 0, "ckc == 0 (sync_regs)");
155*4882a593Smuzhiyun TEST_ASSERT(sync_regs->pp == 0, "pp == 0 (sync_regs)");
156*4882a593Smuzhiyun TEST_ASSERT(sync_regs->gbea == 1, "gbea == 1 (sync_regs)");
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* kvm_run */
159*4882a593Smuzhiyun TEST_ASSERT(run->psw_addr == 0, "psw_addr == 0 (kvm_run)");
160*4882a593Smuzhiyun TEST_ASSERT(run->psw_mask == 0, "psw_mask == 0 (kvm_run)");
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun vcpu_fpu_get(vm, VCPU_ID, &fpu);
163*4882a593Smuzhiyun TEST_ASSERT(!fpu.fpc, "fpc == 0");
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_GBEA, 1);
166*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_PP, 0);
167*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_TODPR, 0);
168*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_CPU_TIMER, 0);
169*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_CLOCK_COMP, 0);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
assert_normal_noclear(void)172*4882a593Smuzhiyun static void assert_normal_noclear(void)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[2] == 0x10, "cr2 == 10 (sync_regs)");
175*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[8] == 1, "cr10 == 1 (sync_regs)");
176*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[10] == 1, "cr10 == 1 (sync_regs)");
177*4882a593Smuzhiyun TEST_ASSERT(sync_regs->crs[11] == -1, "cr11 == -1 (sync_regs)");
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
assert_normal(void)180*4882a593Smuzhiyun static void assert_normal(void)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun test_one_reg(KVM_REG_S390_PFTOKEN, KVM_S390_PFAULT_TOKEN_INVALID);
183*4882a593Smuzhiyun TEST_ASSERT(sync_regs->pft == KVM_S390_PFAULT_TOKEN_INVALID,
184*4882a593Smuzhiyun "pft == 0xff..... (sync_regs)");
185*4882a593Smuzhiyun assert_noirq();
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
inject_irq(int cpu_id)188*4882a593Smuzhiyun static void inject_irq(int cpu_id)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun struct kvm_s390_irq_state irq_state;
191*4882a593Smuzhiyun struct kvm_s390_irq *irq = &buf[0];
192*4882a593Smuzhiyun int irqs;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Inject IRQ */
195*4882a593Smuzhiyun irq_state.len = sizeof(struct kvm_s390_irq);
196*4882a593Smuzhiyun irq_state.buf = (unsigned long)buf;
197*4882a593Smuzhiyun irq->type = KVM_S390_INT_EMERGENCY;
198*4882a593Smuzhiyun irq->u.emerg.code = cpu_id;
199*4882a593Smuzhiyun irqs = _vcpu_ioctl(vm, cpu_id, KVM_S390_SET_IRQ_STATE, &irq_state);
200*4882a593Smuzhiyun TEST_ASSERT(irqs >= 0, "Error injecting EMERGENCY IRQ errno %d\n", errno);
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
test_normal(void)203*4882a593Smuzhiyun static void test_normal(void)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun pr_info("Testing normal reset\n");
206*4882a593Smuzhiyun /* Create VM */
207*4882a593Smuzhiyun vm = vm_create_default(VCPU_ID, 0, guest_code_initial);
208*4882a593Smuzhiyun run = vcpu_state(vm, VCPU_ID);
209*4882a593Smuzhiyun sync_regs = &run->s.regs;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun vcpu_run(vm, VCPU_ID);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun inject_irq(VCPU_ID);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun vcpu_ioctl(vm, VCPU_ID, KVM_S390_NORMAL_RESET, 0);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* must clears */
218*4882a593Smuzhiyun assert_normal();
219*4882a593Smuzhiyun /* must not clears */
220*4882a593Smuzhiyun assert_normal_noclear();
221*4882a593Smuzhiyun assert_initial_noclear();
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun kvm_vm_free(vm);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
test_initial(void)226*4882a593Smuzhiyun static void test_initial(void)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun pr_info("Testing initial reset\n");
229*4882a593Smuzhiyun vm = vm_create_default(VCPU_ID, 0, guest_code_initial);
230*4882a593Smuzhiyun run = vcpu_state(vm, VCPU_ID);
231*4882a593Smuzhiyun sync_regs = &run->s.regs;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun vcpu_run(vm, VCPU_ID);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun inject_irq(VCPU_ID);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun vcpu_ioctl(vm, VCPU_ID, KVM_S390_INITIAL_RESET, 0);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* must clears */
240*4882a593Smuzhiyun assert_normal();
241*4882a593Smuzhiyun assert_initial();
242*4882a593Smuzhiyun /* must not clears */
243*4882a593Smuzhiyun assert_initial_noclear();
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun kvm_vm_free(vm);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
test_clear(void)248*4882a593Smuzhiyun static void test_clear(void)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun pr_info("Testing clear reset\n");
251*4882a593Smuzhiyun vm = vm_create_default(VCPU_ID, 0, guest_code_initial);
252*4882a593Smuzhiyun run = vcpu_state(vm, VCPU_ID);
253*4882a593Smuzhiyun sync_regs = &run->s.regs;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun vcpu_run(vm, VCPU_ID);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun inject_irq(VCPU_ID);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun vcpu_ioctl(vm, VCPU_ID, KVM_S390_CLEAR_RESET, 0);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* must clears */
262*4882a593Smuzhiyun assert_normal();
263*4882a593Smuzhiyun assert_initial();
264*4882a593Smuzhiyun assert_clear();
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun kvm_vm_free(vm);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
main(int argc,char * argv[])269*4882a593Smuzhiyun int main(int argc, char *argv[])
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun setbuf(stdout, NULL); /* Tell stdout not to buffer its content */
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun test_initial();
274*4882a593Smuzhiyun if (kvm_check_cap(KVM_CAP_S390_VCPU_RESETS)) {
275*4882a593Smuzhiyun test_normal();
276*4882a593Smuzhiyun test_clear();
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun return 0;
279*4882a593Smuzhiyun }
280