1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2020 ARM Limited */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * Below definitions may be found in kernel headers, However, they are 6*4882a593Smuzhiyun * redefined here to decouple the MTE selftests compilations from them. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef SEGV_MTEAERR 9*4882a593Smuzhiyun #define SEGV_MTEAERR 8 10*4882a593Smuzhiyun #endif 11*4882a593Smuzhiyun #ifndef SEGV_MTESERR 12*4882a593Smuzhiyun #define SEGV_MTESERR 9 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun #ifndef PROT_MTE 15*4882a593Smuzhiyun #define PROT_MTE 0x20 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun #ifndef HWCAP2_MTE 18*4882a593Smuzhiyun #define HWCAP2_MTE (1 << 18) 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef PR_MTE_TCF_SHIFT 22*4882a593Smuzhiyun #define PR_MTE_TCF_SHIFT 1 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun #ifndef PR_MTE_TCF_NONE 25*4882a593Smuzhiyun #define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #ifndef PR_MTE_TCF_SYNC 28*4882a593Smuzhiyun #define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun #ifndef PR_MTE_TCF_ASYNC 31*4882a593Smuzhiyun #define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) 32*4882a593Smuzhiyun #endif 33*4882a593Smuzhiyun #ifndef PR_MTE_TAG_SHIFT 34*4882a593Smuzhiyun #define PR_MTE_TAG_SHIFT 3 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MTE Hardware feature definitions below. */ 38*4882a593Smuzhiyun #define MT_TAG_SHIFT 56 39*4882a593Smuzhiyun #define MT_TAG_MASK 0xFUL 40*4882a593Smuzhiyun #define MT_FREE_TAG 0x0UL 41*4882a593Smuzhiyun #define MT_GRANULE_SIZE 16 42*4882a593Smuzhiyun #define MT_TAG_COUNT 16 43*4882a593Smuzhiyun #define MT_INCLUDE_TAG_MASK 0xFFFF 44*4882a593Smuzhiyun #define MT_EXCLUDE_TAG_MASK 0x0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define MT_ALIGN_GRANULE (MT_GRANULE_SIZE - 1) 47*4882a593Smuzhiyun #define MT_CLEAR_TAG(x) ((x) & ~(MT_TAG_MASK << MT_TAG_SHIFT)) 48*4882a593Smuzhiyun #define MT_SET_TAG(x, y) ((x) | (y << MT_TAG_SHIFT)) 49*4882a593Smuzhiyun #define MT_FETCH_TAG(x) ((x >> MT_TAG_SHIFT) & (MT_TAG_MASK)) 50*4882a593Smuzhiyun #define MT_ALIGN_UP(x) ((x + MT_ALIGN_GRANULE) & ~(MT_ALIGN_GRANULE)) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MT_PSTATE_TCO_SHIFT 25 53*4882a593Smuzhiyun #define MT_PSTATE_TCO_MASK ~(0x1 << MT_PSTATE_TCO_SHIFT) 54*4882a593Smuzhiyun #define MT_PSTATE_TCO_EN 1 55*4882a593Smuzhiyun #define MT_PSTATE_TCO_DIS 0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MT_EXCLUDE_TAG(x) (1 << (x)) 58*4882a593Smuzhiyun #define MT_INCLUDE_VALID_TAG(x) (MT_INCLUDE_TAG_MASK ^ MT_EXCLUDE_TAG(x)) 59*4882a593Smuzhiyun #define MT_INCLUDE_VALID_TAGS(x) (MT_INCLUDE_TAG_MASK ^ (x)) 60*4882a593Smuzhiyun #define MTE_ALLOW_NON_ZERO_TAG MT_INCLUDE_VALID_TAG(0) 61