1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #if defined(__i386__) || defined(__x86_64__)
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <fcntl.h>
5*4882a593Smuzhiyun #include <stdio.h>
6*4882a593Smuzhiyun #include <unistd.h>
7*4882a593Smuzhiyun #include <stdint.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "helpers/helpers.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /* Intel specific MSRs */
12*4882a593Smuzhiyun #define MSR_IA32_PERF_STATUS 0x198
13*4882a593Smuzhiyun #define MSR_IA32_MISC_ENABLES 0x1a0
14*4882a593Smuzhiyun #define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
15*4882a593Smuzhiyun #define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1ad
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * read_msr
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Will return 0 on success and -1 on failure.
21*4882a593Smuzhiyun * Possible errno values could be:
22*4882a593Smuzhiyun * EFAULT -If the read/write did not fully complete
23*4882a593Smuzhiyun * EIO -If the CPU does not support MSRs
24*4882a593Smuzhiyun * ENXIO -If the CPU does not exist
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun
read_msr(int cpu,unsigned int idx,unsigned long long * val)27*4882a593Smuzhiyun int read_msr(int cpu, unsigned int idx, unsigned long long *val)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun int fd;
30*4882a593Smuzhiyun char msr_file_name[64];
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu);
33*4882a593Smuzhiyun fd = open(msr_file_name, O_RDONLY);
34*4882a593Smuzhiyun if (fd < 0)
35*4882a593Smuzhiyun return -1;
36*4882a593Smuzhiyun if (lseek(fd, idx, SEEK_CUR) == -1)
37*4882a593Smuzhiyun goto err;
38*4882a593Smuzhiyun if (read(fd, val, sizeof *val) != sizeof *val)
39*4882a593Smuzhiyun goto err;
40*4882a593Smuzhiyun close(fd);
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun err:
43*4882a593Smuzhiyun close(fd);
44*4882a593Smuzhiyun return -1;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * write_msr
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * Will return 0 on success and -1 on failure.
51*4882a593Smuzhiyun * Possible errno values could be:
52*4882a593Smuzhiyun * EFAULT -If the read/write did not fully complete
53*4882a593Smuzhiyun * EIO -If the CPU does not support MSRs
54*4882a593Smuzhiyun * ENXIO -If the CPU does not exist
55*4882a593Smuzhiyun */
write_msr(int cpu,unsigned int idx,unsigned long long val)56*4882a593Smuzhiyun int write_msr(int cpu, unsigned int idx, unsigned long long val)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun int fd;
59*4882a593Smuzhiyun char msr_file_name[64];
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun sprintf(msr_file_name, "/dev/cpu/%d/msr", cpu);
62*4882a593Smuzhiyun fd = open(msr_file_name, O_WRONLY);
63*4882a593Smuzhiyun if (fd < 0)
64*4882a593Smuzhiyun return -1;
65*4882a593Smuzhiyun if (lseek(fd, idx, SEEK_CUR) == -1)
66*4882a593Smuzhiyun goto err;
67*4882a593Smuzhiyun if (write(fd, &val, sizeof val) != sizeof val)
68*4882a593Smuzhiyun goto err;
69*4882a593Smuzhiyun close(fd);
70*4882a593Smuzhiyun return 0;
71*4882a593Smuzhiyun err:
72*4882a593Smuzhiyun close(fd);
73*4882a593Smuzhiyun return -1;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
msr_intel_get_perf_bias(unsigned int cpu)76*4882a593Smuzhiyun int msr_intel_get_perf_bias(unsigned int cpu)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun unsigned long long val;
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
82*4882a593Smuzhiyun return -1;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun ret = read_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &val);
85*4882a593Smuzhiyun if (ret)
86*4882a593Smuzhiyun return ret;
87*4882a593Smuzhiyun return val;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
msr_intel_set_perf_bias(unsigned int cpu,unsigned int val)90*4882a593Smuzhiyun int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_PERF_BIAS))
95*4882a593Smuzhiyun return -1;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun ret = write_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, val);
98*4882a593Smuzhiyun if (ret)
99*4882a593Smuzhiyun return ret;
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
msr_intel_get_turbo_ratio(unsigned int cpu)103*4882a593Smuzhiyun unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun unsigned long long val;
106*4882a593Smuzhiyun int ret;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (!(cpupower_cpu_info.caps & CPUPOWER_CAP_HAS_TURBO_RATIO))
109*4882a593Smuzhiyun return -1;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ret = read_msr(cpu, MSR_NEHALEM_TURBO_RATIO_LIMIT, &val);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun return ret;
114*4882a593Smuzhiyun return val;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun #endif
117