1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * intel_pt.h: Intel Processor Trace support 4*4882a593Smuzhiyun * Copyright (c) 2013-2015, Intel Corporation. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef INCLUDE__PERF_INTEL_PT_H__ 8*4882a593Smuzhiyun #define INCLUDE__PERF_INTEL_PT_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define INTEL_PT_PMU_NAME "intel_pt" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum { 13*4882a593Smuzhiyun INTEL_PT_PMU_TYPE, 14*4882a593Smuzhiyun INTEL_PT_TIME_SHIFT, 15*4882a593Smuzhiyun INTEL_PT_TIME_MULT, 16*4882a593Smuzhiyun INTEL_PT_TIME_ZERO, 17*4882a593Smuzhiyun INTEL_PT_CAP_USER_TIME_ZERO, 18*4882a593Smuzhiyun INTEL_PT_TSC_BIT, 19*4882a593Smuzhiyun INTEL_PT_NORETCOMP_BIT, 20*4882a593Smuzhiyun INTEL_PT_HAVE_SCHED_SWITCH, 21*4882a593Smuzhiyun INTEL_PT_SNAPSHOT_MODE, 22*4882a593Smuzhiyun INTEL_PT_PER_CPU_MMAPS, 23*4882a593Smuzhiyun INTEL_PT_MTC_BIT, 24*4882a593Smuzhiyun INTEL_PT_MTC_FREQ_BITS, 25*4882a593Smuzhiyun INTEL_PT_TSC_CTC_N, 26*4882a593Smuzhiyun INTEL_PT_TSC_CTC_D, 27*4882a593Smuzhiyun INTEL_PT_CYC_BIT, 28*4882a593Smuzhiyun INTEL_PT_MAX_NONTURBO_RATIO, 29*4882a593Smuzhiyun INTEL_PT_FILTER_STR_LEN, 30*4882a593Smuzhiyun INTEL_PT_AUXTRACE_PRIV_MAX, 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct auxtrace_record; 34*4882a593Smuzhiyun struct perf_tool; 35*4882a593Smuzhiyun union perf_event; 36*4882a593Smuzhiyun struct perf_session; 37*4882a593Smuzhiyun struct perf_event_attr; 38*4882a593Smuzhiyun struct perf_pmu; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct auxtrace_record *intel_pt_recording_init(int *err); 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun int intel_pt_process_auxtrace_info(union perf_event *event, 43*4882a593Smuzhiyun struct perf_session *session); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct perf_event_attr *intel_pt_pmu_default_config(struct perf_pmu *pmu); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48