xref: /OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun[
2*4882a593Smuzhiyun    {
3*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
4*4882a593Smuzhiyun        "Counter": "0,1,2,3",
5*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
6*4882a593Smuzhiyun        "EventCode": "0xC7",
7*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
8*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
9*4882a593Smuzhiyun        "UMask": "0x4"
10*4882a593Smuzhiyun    },
11*4882a593Smuzhiyun    {
12*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
13*4882a593Smuzhiyun        "Counter": "0,1,2,3",
14*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
15*4882a593Smuzhiyun        "EventCode": "0xC7",
16*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
17*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
18*4882a593Smuzhiyun        "UMask": "0x40"
19*4882a593Smuzhiyun    },
20*4882a593Smuzhiyun    {
21*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
22*4882a593Smuzhiyun        "Counter": "0,1,2,3",
23*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
24*4882a593Smuzhiyun        "EventCode": "0xC7",
25*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
26*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
27*4882a593Smuzhiyun        "UMask": "0x2"
28*4882a593Smuzhiyun    },
29*4882a593Smuzhiyun    {
30*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
31*4882a593Smuzhiyun        "Counter": "0,1,2,3",
32*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
33*4882a593Smuzhiyun        "EventCode": "0xC7",
34*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
35*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
36*4882a593Smuzhiyun        "UMask": "0x10"
37*4882a593Smuzhiyun    },
38*4882a593Smuzhiyun    {
39*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.",
40*4882a593Smuzhiyun        "Counter": "0,1,2,3",
41*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
42*4882a593Smuzhiyun        "EventCode": "0xC7",
43*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
44*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
45*4882a593Smuzhiyun        "UMask": "0x80"
46*4882a593Smuzhiyun    },
47*4882a593Smuzhiyun    {
48*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
49*4882a593Smuzhiyun        "Counter": "0,1,2,3",
50*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
51*4882a593Smuzhiyun        "EventCode": "0xC7",
52*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
53*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
54*4882a593Smuzhiyun        "UMask": "0x20"
55*4882a593Smuzhiyun    },
56*4882a593Smuzhiyun    {
57*4882a593Smuzhiyun        "BriefDescription": "Cycles with any input/output SSE or FP assist",
58*4882a593Smuzhiyun        "Counter": "0,1,2,3",
59*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
60*4882a593Smuzhiyun        "CounterMask": "1",
61*4882a593Smuzhiyun        "EventCode": "0xCA",
62*4882a593Smuzhiyun        "EventName": "FP_ASSIST.ANY",
63*4882a593Smuzhiyun        "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
64*4882a593Smuzhiyun        "SampleAfterValue": "100003",
65*4882a593Smuzhiyun        "UMask": "0x1e"
66*4882a593Smuzhiyun    },
67*4882a593Smuzhiyun    {
68*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
69*4882a593Smuzhiyun        "Counter": "0,1,2,3",
70*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
71*4882a593Smuzhiyun        "EventCode": "0xC7",
72*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
73*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
74*4882a593Smuzhiyun        "UMask": "0x1"
75*4882a593Smuzhiyun    },
76*4882a593Smuzhiyun    {
77*4882a593Smuzhiyun        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
78*4882a593Smuzhiyun        "Counter": "0,1,2,3",
79*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7",
80*4882a593Smuzhiyun        "EventCode": "0xC7",
81*4882a593Smuzhiyun        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
82*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
83*4882a593Smuzhiyun        "UMask": "0x8"
84*4882a593Smuzhiyun    }
85*4882a593Smuzhiyun]