1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "EventCode": "0xC7", 4*4882a593Smuzhiyun "Counter": "0,1,2,3", 5*4882a593Smuzhiyun "UMask": "0x1", 6*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 7*4882a593Smuzhiyun "SampleAfterValue": "2000003", 8*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 9*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 10*4882a593Smuzhiyun }, 11*4882a593Smuzhiyun { 12*4882a593Smuzhiyun "EventCode": "0xC7", 13*4882a593Smuzhiyun "Counter": "0,1,2,3", 14*4882a593Smuzhiyun "UMask": "0x2", 15*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 16*4882a593Smuzhiyun "SampleAfterValue": "2000003", 17*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 18*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 19*4882a593Smuzhiyun }, 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun "EventCode": "0xC7", 22*4882a593Smuzhiyun "Counter": "0,1,2,3", 23*4882a593Smuzhiyun "UMask": "0x4", 24*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 25*4882a593Smuzhiyun "SampleAfterValue": "2000003", 26*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 27*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 28*4882a593Smuzhiyun }, 29*4882a593Smuzhiyun { 30*4882a593Smuzhiyun "EventCode": "0xC7", 31*4882a593Smuzhiyun "Counter": "0,1,2,3", 32*4882a593Smuzhiyun "UMask": "0x8", 33*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 34*4882a593Smuzhiyun "SampleAfterValue": "2000003", 35*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 36*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 37*4882a593Smuzhiyun }, 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun "EventCode": "0xC7", 40*4882a593Smuzhiyun "Counter": "0,1,2,3", 41*4882a593Smuzhiyun "UMask": "0x10", 42*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 43*4882a593Smuzhiyun "SampleAfterValue": "2000003", 44*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 45*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 46*4882a593Smuzhiyun }, 47*4882a593Smuzhiyun { 48*4882a593Smuzhiyun "EventCode": "0xC7", 49*4882a593Smuzhiyun "Counter": "0,1,2,3", 50*4882a593Smuzhiyun "UMask": "0x20", 51*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 52*4882a593Smuzhiyun "SampleAfterValue": "2000003", 53*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 54*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 55*4882a593Smuzhiyun }, 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", 58*4882a593Smuzhiyun "EventCode": "0xCA", 59*4882a593Smuzhiyun "Counter": "0,1,2,3", 60*4882a593Smuzhiyun "UMask": "0x1e", 61*4882a593Smuzhiyun "EventName": "FP_ASSIST.ANY", 62*4882a593Smuzhiyun "SampleAfterValue": "100003", 63*4882a593Smuzhiyun "BriefDescription": "Cycles with any input/output SSE or FP assist", 64*4882a593Smuzhiyun "CounterMask": "1", 65*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 66*4882a593Smuzhiyun } 67*4882a593Smuzhiyun]