1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "EventCode": "0x17", 4*4882a593Smuzhiyun "Counter": "0,1,2,3", 5*4882a593Smuzhiyun "UMask": "0x1", 6*4882a593Smuzhiyun "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", 7*4882a593Smuzhiyun "SampleAfterValue": "2000003", 8*4882a593Smuzhiyun "BriefDescription": "Valid instructions written to IQ per cycle.", 9*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 10*4882a593Smuzhiyun }, 11*4882a593Smuzhiyun { 12*4882a593Smuzhiyun "EventCode": "0x5C", 13*4882a593Smuzhiyun "Counter": "0,1,2,3", 14*4882a593Smuzhiyun "UMask": "0x1", 15*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING0", 16*4882a593Smuzhiyun "SampleAfterValue": "2000003", 17*4882a593Smuzhiyun "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", 18*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 19*4882a593Smuzhiyun }, 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun "EventCode": "0x5C", 22*4882a593Smuzhiyun "Counter": "0,1,2,3", 23*4882a593Smuzhiyun "UMask": "0x1", 24*4882a593Smuzhiyun "EdgeDetect": "1", 25*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING0_TRANS", 26*4882a593Smuzhiyun "SampleAfterValue": "100007", 27*4882a593Smuzhiyun "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", 28*4882a593Smuzhiyun "CounterMask": "1", 29*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 30*4882a593Smuzhiyun }, 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun "EventCode": "0x5C", 33*4882a593Smuzhiyun "Counter": "0,1,2,3", 34*4882a593Smuzhiyun "UMask": "0x2", 35*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING123", 36*4882a593Smuzhiyun "SampleAfterValue": "2000003", 37*4882a593Smuzhiyun "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", 38*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 39*4882a593Smuzhiyun }, 40*4882a593Smuzhiyun { 41*4882a593Smuzhiyun "EventCode": "0x4E", 42*4882a593Smuzhiyun "Counter": "0,1,2,3", 43*4882a593Smuzhiyun "UMask": "0x2", 44*4882a593Smuzhiyun "EventName": "HW_PRE_REQ.DL1_MISS", 45*4882a593Smuzhiyun "SampleAfterValue": "2000003", 46*4882a593Smuzhiyun "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", 47*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 48*4882a593Smuzhiyun }, 49*4882a593Smuzhiyun { 50*4882a593Smuzhiyun "EventCode": "0x63", 51*4882a593Smuzhiyun "Counter": "0,1,2,3", 52*4882a593Smuzhiyun "UMask": "0x1", 53*4882a593Smuzhiyun "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 54*4882a593Smuzhiyun "SampleAfterValue": "2000003", 55*4882a593Smuzhiyun "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", 56*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun]