1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "CollectPEBSRecord": "2", 4*4882a593Smuzhiyun "PublicDescription": "Counts all microcode Floating Point assists.", 5*4882a593Smuzhiyun "EventCode": "0xC1", 6*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 7*4882a593Smuzhiyun "UMask": "0x2", 8*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 9*4882a593Smuzhiyun "EventName": "ASSISTS.FP", 10*4882a593Smuzhiyun "SampleAfterValue": "100003", 11*4882a593Smuzhiyun "BriefDescription": "Counts all microcode FP assists.", 12*4882a593Smuzhiyun "CounterMask": "1" 13*4882a593Smuzhiyun }, 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun "CollectPEBSRecord": "2", 16*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 17*4882a593Smuzhiyun "EventCode": "0xc7", 18*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 19*4882a593Smuzhiyun "UMask": "0x1", 20*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 21*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 22*4882a593Smuzhiyun "SampleAfterValue": "2000003", 23*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 24*4882a593Smuzhiyun }, 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun "CollectPEBSRecord": "2", 27*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 28*4882a593Smuzhiyun "EventCode": "0xc7", 29*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 30*4882a593Smuzhiyun "UMask": "0x2", 31*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 32*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 33*4882a593Smuzhiyun "SampleAfterValue": "2000003", 34*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 35*4882a593Smuzhiyun }, 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun "CollectPEBSRecord": "2", 38*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 39*4882a593Smuzhiyun "EventCode": "0xc7", 40*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 41*4882a593Smuzhiyun "UMask": "0x4", 42*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 43*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 44*4882a593Smuzhiyun "SampleAfterValue": "2000003", 45*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 46*4882a593Smuzhiyun }, 47*4882a593Smuzhiyun { 48*4882a593Smuzhiyun "CollectPEBSRecord": "2", 49*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 50*4882a593Smuzhiyun "EventCode": "0xc7", 51*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 52*4882a593Smuzhiyun "UMask": "0x8", 53*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 54*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 55*4882a593Smuzhiyun "SampleAfterValue": "2000003", 56*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 57*4882a593Smuzhiyun }, 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun "CollectPEBSRecord": "2", 60*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 61*4882a593Smuzhiyun "EventCode": "0xc7", 62*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 63*4882a593Smuzhiyun "UMask": "0x10", 64*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 65*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 66*4882a593Smuzhiyun "SampleAfterValue": "2000003", 67*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 68*4882a593Smuzhiyun }, 69*4882a593Smuzhiyun { 70*4882a593Smuzhiyun "CollectPEBSRecord": "2", 71*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 72*4882a593Smuzhiyun "EventCode": "0xc7", 73*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 74*4882a593Smuzhiyun "UMask": "0x20", 75*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 76*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 77*4882a593Smuzhiyun "SampleAfterValue": "2000003", 78*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 79*4882a593Smuzhiyun }, 80*4882a593Smuzhiyun { 81*4882a593Smuzhiyun "CollectPEBSRecord": "2", 82*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 83*4882a593Smuzhiyun "EventCode": "0xc7", 84*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 85*4882a593Smuzhiyun "UMask": "0x40", 86*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 87*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", 88*4882a593Smuzhiyun "SampleAfterValue": "2000003", 89*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 90*4882a593Smuzhiyun }, 91*4882a593Smuzhiyun { 92*4882a593Smuzhiyun "CollectPEBSRecord": "2", 93*4882a593Smuzhiyun "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 94*4882a593Smuzhiyun "EventCode": "0xc7", 95*4882a593Smuzhiyun "Counter": "0,1,2,3,4,5,6,7", 96*4882a593Smuzhiyun "UMask": "0x80", 97*4882a593Smuzhiyun "PEBScounters": "0,1,2,3,4,5,6,7", 98*4882a593Smuzhiyun "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", 99*4882a593Smuzhiyun "SampleAfterValue": "2000003", 100*4882a593Smuzhiyun "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." 101*4882a593Smuzhiyun } 102*4882a593Smuzhiyun]