xref: /OK3568_Linux_fs/kernel/tools/perf/pmu-events/arch/x86/haswell/other.json (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun[
2*4882a593Smuzhiyun    {
3*4882a593Smuzhiyun        "PublicDescription": "Unhalted core cycles when the thread is in ring 0.",
4*4882a593Smuzhiyun        "EventCode": "0x5C",
5*4882a593Smuzhiyun        "Counter": "0,1,2,3",
6*4882a593Smuzhiyun        "UMask": "0x1",
7*4882a593Smuzhiyun        "EventName": "CPL_CYCLES.RING0",
8*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
9*4882a593Smuzhiyun        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
10*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7"
11*4882a593Smuzhiyun    },
12*4882a593Smuzhiyun    {
13*4882a593Smuzhiyun        "EventCode": "0x5C",
14*4882a593Smuzhiyun        "Counter": "0,1,2,3",
15*4882a593Smuzhiyun        "UMask": "0x1",
16*4882a593Smuzhiyun        "EdgeDetect": "1",
17*4882a593Smuzhiyun        "EventName": "CPL_CYCLES.RING0_TRANS",
18*4882a593Smuzhiyun        "SampleAfterValue": "100003",
19*4882a593Smuzhiyun        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
20*4882a593Smuzhiyun        "CounterMask": "1",
21*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7"
22*4882a593Smuzhiyun    },
23*4882a593Smuzhiyun    {
24*4882a593Smuzhiyun        "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.",
25*4882a593Smuzhiyun        "EventCode": "0x5C",
26*4882a593Smuzhiyun        "Counter": "0,1,2,3",
27*4882a593Smuzhiyun        "UMask": "0x2",
28*4882a593Smuzhiyun        "EventName": "CPL_CYCLES.RING123",
29*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
30*4882a593Smuzhiyun        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
31*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7"
32*4882a593Smuzhiyun    },
33*4882a593Smuzhiyun    {
34*4882a593Smuzhiyun        "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.",
35*4882a593Smuzhiyun        "EventCode": "0x63",
36*4882a593Smuzhiyun        "Counter": "0,1,2,3",
37*4882a593Smuzhiyun        "UMask": "0x1",
38*4882a593Smuzhiyun        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
39*4882a593Smuzhiyun        "SampleAfterValue": "2000003",
40*4882a593Smuzhiyun        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
41*4882a593Smuzhiyun        "CounterHTOff": "0,1,2,3,4,5,6,7"
42*4882a593Smuzhiyun    }
43*4882a593Smuzhiyun]