1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "BriefDescription": "Instructions Per Cycle (per logical thread)", 4*4882a593Smuzhiyun "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", 5*4882a593Smuzhiyun "MetricGroup": "TopDownL1", 6*4882a593Smuzhiyun "MetricName": "IPC" 7*4882a593Smuzhiyun }, 8*4882a593Smuzhiyun { 9*4882a593Smuzhiyun "BriefDescription": "Uops Per Instruction", 10*4882a593Smuzhiyun "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", 11*4882a593Smuzhiyun "MetricGroup": "Pipeline", 12*4882a593Smuzhiyun "MetricName": "UPI" 13*4882a593Smuzhiyun }, 14*4882a593Smuzhiyun { 15*4882a593Smuzhiyun "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions", 16*4882a593Smuzhiyun "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", 17*4882a593Smuzhiyun "MetricGroup": "Frontend", 18*4882a593Smuzhiyun "MetricName": "IFetch_Line_Utilization" 19*4882a593Smuzhiyun }, 20*4882a593Smuzhiyun { 21*4882a593Smuzhiyun "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)", 22*4882a593Smuzhiyun "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", 23*4882a593Smuzhiyun "MetricGroup": "DSB; Frontend_Bandwidth", 24*4882a593Smuzhiyun "MetricName": "DSB_Coverage" 25*4882a593Smuzhiyun }, 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun "BriefDescription": "Cycles Per Instruction (threaded)", 28*4882a593Smuzhiyun "MetricExpr": "1 / INST_RETIRED.ANY / cycles", 29*4882a593Smuzhiyun "MetricGroup": "Pipeline;Summary", 30*4882a593Smuzhiyun "MetricName": "CPI" 31*4882a593Smuzhiyun }, 32*4882a593Smuzhiyun { 33*4882a593Smuzhiyun "BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.", 34*4882a593Smuzhiyun "MetricExpr": "CPU_CLK_UNHALTED.THREAD", 35*4882a593Smuzhiyun "MetricGroup": "Summary", 36*4882a593Smuzhiyun "MetricName": "CLKS" 37*4882a593Smuzhiyun }, 38*4882a593Smuzhiyun { 39*4882a593Smuzhiyun "BriefDescription": "Total issue-pipeline slots", 40*4882a593Smuzhiyun "MetricExpr": "4*( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", 41*4882a593Smuzhiyun "MetricGroup": "TopDownL1", 42*4882a593Smuzhiyun "MetricName": "SLOTS" 43*4882a593Smuzhiyun }, 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun "BriefDescription": "Total number of retired Instructions", 46*4882a593Smuzhiyun "MetricExpr": "INST_RETIRED.ANY", 47*4882a593Smuzhiyun "MetricGroup": "Summary", 48*4882a593Smuzhiyun "MetricName": "Instructions" 49*4882a593Smuzhiyun }, 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun "BriefDescription": "Instructions Per Cycle (per physical core)", 52*4882a593Smuzhiyun "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", 53*4882a593Smuzhiyun "MetricGroup": "SMT", 54*4882a593Smuzhiyun "MetricName": "CoreIPC" 55*4882a593Smuzhiyun }, 56*4882a593Smuzhiyun { 57*4882a593Smuzhiyun "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", 58*4882a593Smuzhiyun "MetricExpr": "UOPS_EXECUTED.THREAD / ( cpu@uops_executed.core\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", 59*4882a593Smuzhiyun "MetricGroup": "Pipeline;Ports_Utilization", 60*4882a593Smuzhiyun "MetricName": "ILP" 61*4882a593Smuzhiyun }, 62*4882a593Smuzhiyun { 63*4882a593Smuzhiyun "BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)", 64*4882a593Smuzhiyun "MetricExpr": "2* ( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7* ITLB_MISSES.WALK_COMPLETED ) ) / RS_EVENTS.EMPTY_END", 65*4882a593Smuzhiyun "MetricGroup": "Unknown_Branches", 66*4882a593Smuzhiyun "MetricName": "BAClear_Cost" 67*4882a593Smuzhiyun }, 68*4882a593Smuzhiyun { 69*4882a593Smuzhiyun "BriefDescription": "Core actual clocks when any thread is active on the physical core", 70*4882a593Smuzhiyun "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD", 71*4882a593Smuzhiyun "MetricGroup": "SMT", 72*4882a593Smuzhiyun "MetricName": "CORE_CLKS" 73*4882a593Smuzhiyun }, 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads", 76*4882a593Smuzhiyun "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", 77*4882a593Smuzhiyun "MetricGroup": "Memory_Bound;Memory_Lat", 78*4882a593Smuzhiyun "MetricName": "Load_Miss_Real_Latency" 79*4882a593Smuzhiyun }, 80*4882a593Smuzhiyun { 81*4882a593Smuzhiyun "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)", 82*4882a593Smuzhiyun "MetricExpr": "L1D_PEND_MISS.PENDING / ( cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES", 83*4882a593Smuzhiyun "MetricGroup": "Memory_Bound;Memory_BW", 84*4882a593Smuzhiyun "MetricName": "MLP" 85*4882a593Smuzhiyun }, 86*4882a593Smuzhiyun { 87*4882a593Smuzhiyun "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", 88*4882a593Smuzhiyun "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", 89*4882a593Smuzhiyun "MetricGroup": "TLB", 90*4882a593Smuzhiyun "MetricName": "Page_Walks_Utilization" 91*4882a593Smuzhiyun }, 92*4882a593Smuzhiyun { 93*4882a593Smuzhiyun "BriefDescription": "Average CPU Utilization", 94*4882a593Smuzhiyun "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", 95*4882a593Smuzhiyun "MetricGroup": "Summary", 96*4882a593Smuzhiyun "MetricName": "CPU_Utilization" 97*4882a593Smuzhiyun }, 98*4882a593Smuzhiyun { 99*4882a593Smuzhiyun "BriefDescription": "Giga Floating Point Operations Per Second", 100*4882a593Smuzhiyun "MetricExpr": "( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 / duration_time", 101*4882a593Smuzhiyun "MetricGroup": "FLOPS;Summary", 102*4882a593Smuzhiyun "MetricName": "GFLOPs" 103*4882a593Smuzhiyun }, 104*4882a593Smuzhiyun { 105*4882a593Smuzhiyun "BriefDescription": "Average Frequency Utilization relative nominal frequency", 106*4882a593Smuzhiyun "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", 107*4882a593Smuzhiyun "MetricGroup": "Power", 108*4882a593Smuzhiyun "MetricName": "Turbo_Utilization" 109*4882a593Smuzhiyun }, 110*4882a593Smuzhiyun { 111*4882a593Smuzhiyun "BriefDescription": "Fraction of cycles where both hardware threads were active", 112*4882a593Smuzhiyun "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", 113*4882a593Smuzhiyun "MetricGroup": "SMT;Summary", 114*4882a593Smuzhiyun "MetricName": "SMT_2T_Utilization" 115*4882a593Smuzhiyun }, 116*4882a593Smuzhiyun { 117*4882a593Smuzhiyun "BriefDescription": "Fraction of cycles spent in Kernel mode", 118*4882a593Smuzhiyun "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", 119*4882a593Smuzhiyun "MetricGroup": "Summary", 120*4882a593Smuzhiyun "MetricName": "Kernel_Utilization" 121*4882a593Smuzhiyun }, 122*4882a593Smuzhiyun { 123*4882a593Smuzhiyun "BriefDescription": "C3 residency percent per core", 124*4882a593Smuzhiyun "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", 125*4882a593Smuzhiyun "MetricGroup": "Power", 126*4882a593Smuzhiyun "MetricName": "C3_Core_Residency" 127*4882a593Smuzhiyun }, 128*4882a593Smuzhiyun { 129*4882a593Smuzhiyun "BriefDescription": "C6 residency percent per core", 130*4882a593Smuzhiyun "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", 131*4882a593Smuzhiyun "MetricGroup": "Power", 132*4882a593Smuzhiyun "MetricName": "C6_Core_Residency" 133*4882a593Smuzhiyun }, 134*4882a593Smuzhiyun { 135*4882a593Smuzhiyun "BriefDescription": "C7 residency percent per core", 136*4882a593Smuzhiyun "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", 137*4882a593Smuzhiyun "MetricGroup": "Power", 138*4882a593Smuzhiyun "MetricName": "C7_Core_Residency" 139*4882a593Smuzhiyun }, 140*4882a593Smuzhiyun { 141*4882a593Smuzhiyun "BriefDescription": "C2 residency percent per package", 142*4882a593Smuzhiyun "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", 143*4882a593Smuzhiyun "MetricGroup": "Power", 144*4882a593Smuzhiyun "MetricName": "C2_Pkg_Residency" 145*4882a593Smuzhiyun }, 146*4882a593Smuzhiyun { 147*4882a593Smuzhiyun "BriefDescription": "C3 residency percent per package", 148*4882a593Smuzhiyun "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", 149*4882a593Smuzhiyun "MetricGroup": "Power", 150*4882a593Smuzhiyun "MetricName": "C3_Pkg_Residency" 151*4882a593Smuzhiyun }, 152*4882a593Smuzhiyun { 153*4882a593Smuzhiyun "BriefDescription": "C6 residency percent per package", 154*4882a593Smuzhiyun "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", 155*4882a593Smuzhiyun "MetricGroup": "Power", 156*4882a593Smuzhiyun "MetricName": "C6_Pkg_Residency" 157*4882a593Smuzhiyun }, 158*4882a593Smuzhiyun { 159*4882a593Smuzhiyun "BriefDescription": "C7 residency percent per package", 160*4882a593Smuzhiyun "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", 161*4882a593Smuzhiyun "MetricGroup": "Power", 162*4882a593Smuzhiyun "MetricName": "C7_Pkg_Residency" 163*4882a593Smuzhiyun } 164*4882a593Smuzhiyun] 165