1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", 4*4882a593Smuzhiyun "EventCode": "0x5C", 5*4882a593Smuzhiyun "Counter": "0,1,2,3", 6*4882a593Smuzhiyun "UMask": "0x1", 7*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING0", 8*4882a593Smuzhiyun "SampleAfterValue": "2000003", 9*4882a593Smuzhiyun "BriefDescription": "Unhalted core cycles when the thread is in ring 0", 10*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 11*4882a593Smuzhiyun }, 12*4882a593Smuzhiyun { 13*4882a593Smuzhiyun "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", 14*4882a593Smuzhiyun "EventCode": "0x5C", 15*4882a593Smuzhiyun "Counter": "0,1,2,3", 16*4882a593Smuzhiyun "UMask": "0x1", 17*4882a593Smuzhiyun "EdgeDetect": "1", 18*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING0_TRANS", 19*4882a593Smuzhiyun "SampleAfterValue": "100007", 20*4882a593Smuzhiyun "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", 21*4882a593Smuzhiyun "CounterMask": "1", 22*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 23*4882a593Smuzhiyun }, 24*4882a593Smuzhiyun { 25*4882a593Smuzhiyun "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", 26*4882a593Smuzhiyun "EventCode": "0x5C", 27*4882a593Smuzhiyun "Counter": "0,1,2,3", 28*4882a593Smuzhiyun "UMask": "0x2", 29*4882a593Smuzhiyun "EventName": "CPL_CYCLES.RING123", 30*4882a593Smuzhiyun "SampleAfterValue": "2000003", 31*4882a593Smuzhiyun "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", 32*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 33*4882a593Smuzhiyun }, 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", 36*4882a593Smuzhiyun "EventCode": "0x63", 37*4882a593Smuzhiyun "Counter": "0,1,2,3", 38*4882a593Smuzhiyun "UMask": "0x1", 39*4882a593Smuzhiyun "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", 40*4882a593Smuzhiyun "SampleAfterValue": "2000003", 41*4882a593Smuzhiyun "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", 42*4882a593Smuzhiyun "CounterHTOff": "0,1,2,3,4,5,6,7" 43*4882a593Smuzhiyun } 44*4882a593Smuzhiyun]