1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "EventCode": "0x80", 4*4882a593Smuzhiyun "Counter": "0,1", 5*4882a593Smuzhiyun "UMask": "0x3", 6*4882a593Smuzhiyun "EventName": "ICACHE.ACCESSES", 7*4882a593Smuzhiyun "SampleAfterValue": "200000", 8*4882a593Smuzhiyun "BriefDescription": "Instruction fetches." 9*4882a593Smuzhiyun }, 10*4882a593Smuzhiyun { 11*4882a593Smuzhiyun "EventCode": "0x80", 12*4882a593Smuzhiyun "Counter": "0,1", 13*4882a593Smuzhiyun "UMask": "0x1", 14*4882a593Smuzhiyun "EventName": "ICACHE.HIT", 15*4882a593Smuzhiyun "SampleAfterValue": "200000", 16*4882a593Smuzhiyun "BriefDescription": "Icache hit" 17*4882a593Smuzhiyun }, 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun "EventCode": "0x80", 20*4882a593Smuzhiyun "Counter": "0,1", 21*4882a593Smuzhiyun "UMask": "0x2", 22*4882a593Smuzhiyun "EventName": "ICACHE.MISSES", 23*4882a593Smuzhiyun "SampleAfterValue": "200000", 24*4882a593Smuzhiyun "BriefDescription": "Icache miss" 25*4882a593Smuzhiyun }, 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun "EventCode": "0x86", 28*4882a593Smuzhiyun "Counter": "0,1", 29*4882a593Smuzhiyun "UMask": "0x1", 30*4882a593Smuzhiyun "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", 31*4882a593Smuzhiyun "SampleAfterValue": "2000000", 32*4882a593Smuzhiyun "BriefDescription": "Cycles during which instruction fetches are stalled." 33*4882a593Smuzhiyun }, 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun "EventCode": "0x87", 36*4882a593Smuzhiyun "Counter": "0,1", 37*4882a593Smuzhiyun "UMask": "0x1", 38*4882a593Smuzhiyun "EventName": "DECODE_STALL.PFB_EMPTY", 39*4882a593Smuzhiyun "SampleAfterValue": "2000000", 40*4882a593Smuzhiyun "BriefDescription": "Decode stall due to PFB empty" 41*4882a593Smuzhiyun }, 42*4882a593Smuzhiyun { 43*4882a593Smuzhiyun "EventCode": "0x87", 44*4882a593Smuzhiyun "Counter": "0,1", 45*4882a593Smuzhiyun "UMask": "0x2", 46*4882a593Smuzhiyun "EventName": "DECODE_STALL.IQ_FULL", 47*4882a593Smuzhiyun "SampleAfterValue": "2000000", 48*4882a593Smuzhiyun "BriefDescription": "Decode stall due to IQ full" 49*4882a593Smuzhiyun }, 50*4882a593Smuzhiyun { 51*4882a593Smuzhiyun "EventCode": "0xAA", 52*4882a593Smuzhiyun "Counter": "0,1", 53*4882a593Smuzhiyun "UMask": "0x1", 54*4882a593Smuzhiyun "EventName": "MACRO_INSTS.NON_CISC_DECODED", 55*4882a593Smuzhiyun "SampleAfterValue": "2000000", 56*4882a593Smuzhiyun "BriefDescription": "Non-CISC nacro instructions decoded" 57*4882a593Smuzhiyun }, 58*4882a593Smuzhiyun { 59*4882a593Smuzhiyun "EventCode": "0xAA", 60*4882a593Smuzhiyun "Counter": "0,1", 61*4882a593Smuzhiyun "UMask": "0x2", 62*4882a593Smuzhiyun "EventName": "MACRO_INSTS.CISC_DECODED", 63*4882a593Smuzhiyun "SampleAfterValue": "2000000", 64*4882a593Smuzhiyun "BriefDescription": "CISC macro instructions decoded" 65*4882a593Smuzhiyun }, 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun "EventCode": "0xAA", 68*4882a593Smuzhiyun "Counter": "0,1", 69*4882a593Smuzhiyun "UMask": "0x3", 70*4882a593Smuzhiyun "EventName": "MACRO_INSTS.ALL_DECODED", 71*4882a593Smuzhiyun "SampleAfterValue": "2000000", 72*4882a593Smuzhiyun "BriefDescription": "All Instructions decoded" 73*4882a593Smuzhiyun }, 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun "EventCode": "0xA9", 76*4882a593Smuzhiyun "Counter": "0,1", 77*4882a593Smuzhiyun "UMask": "0x1", 78*4882a593Smuzhiyun "EventName": "UOPS.MS_CYCLES", 79*4882a593Smuzhiyun "SampleAfterValue": "2000000", 80*4882a593Smuzhiyun "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", 81*4882a593Smuzhiyun "CounterMask": "1" 82*4882a593Smuzhiyun } 83*4882a593Smuzhiyun]