1*4882a593Smuzhiyun[ 2*4882a593Smuzhiyun { 3*4882a593Smuzhiyun "EventCode": "0x1415A", 4*4882a593Smuzhiyun "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", 5*4882a593Smuzhiyun "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load" 6*4882a593Smuzhiyun }, 7*4882a593Smuzhiyun { 8*4882a593Smuzhiyun "EventCode": "0x10058", 9*4882a593Smuzhiyun "EventName": "PM_MEM_LOC_THRESH_IFU", 10*4882a593Smuzhiyun "BriefDescription": "Local Memory above threshold for IFU speculation control" 11*4882a593Smuzhiyun }, 12*4882a593Smuzhiyun { 13*4882a593Smuzhiyun "EventCode": "0x2D028", 14*4882a593Smuzhiyun "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", 15*4882a593Smuzhiyun "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache" 16*4882a593Smuzhiyun }, 17*4882a593Smuzhiyun { 18*4882a593Smuzhiyun "EventCode": "0x30012", 19*4882a593Smuzhiyun "EventName": "PM_FLUSH_COMPLETION", 20*4882a593Smuzhiyun "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush" 21*4882a593Smuzhiyun }, 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun "EventCode": "0x2D154", 24*4882a593Smuzhiyun "EventName": "PM_MRK_DERAT_MISS_64K", 25*4882a593Smuzhiyun "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K" 26*4882a593Smuzhiyun }, 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun "EventCode": "0x4016E", 29*4882a593Smuzhiyun "EventName": "PM_THRESH_NOT_MET", 30*4882a593Smuzhiyun "BriefDescription": "Threshold counter did not meet threshold" 31*4882a593Smuzhiyun } 32*4882a593Smuzhiyun] 33