1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef ARCH_PERF_REGS_H 5*4882a593Smuzhiyun #define ARCH_PERF_REGS_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <stdlib.h> 8*4882a593Smuzhiyun #include <linux/types.h> 9*4882a593Smuzhiyun #include <asm/perf_regs.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PERF_REGS_MASK ((1ULL << PERF_REG_RISCV_MAX) - 1) 12*4882a593Smuzhiyun #define PERF_REGS_MAX PERF_REG_RISCV_MAX 13*4882a593Smuzhiyun #if __riscv_xlen == 64 14*4882a593Smuzhiyun #define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_64 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun #define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_32 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define PERF_REG_IP PERF_REG_RISCV_PC 20*4882a593Smuzhiyun #define PERF_REG_SP PERF_REG_RISCV_SP 21*4882a593Smuzhiyun __perf_reg_name(int id)22*4882a593Smuzhiyunstatic inline const char *__perf_reg_name(int id) 23*4882a593Smuzhiyun { 24*4882a593Smuzhiyun switch (id) { 25*4882a593Smuzhiyun case PERF_REG_RISCV_PC: 26*4882a593Smuzhiyun return "pc"; 27*4882a593Smuzhiyun case PERF_REG_RISCV_RA: 28*4882a593Smuzhiyun return "ra"; 29*4882a593Smuzhiyun case PERF_REG_RISCV_SP: 30*4882a593Smuzhiyun return "sp"; 31*4882a593Smuzhiyun case PERF_REG_RISCV_GP: 32*4882a593Smuzhiyun return "gp"; 33*4882a593Smuzhiyun case PERF_REG_RISCV_TP: 34*4882a593Smuzhiyun return "tp"; 35*4882a593Smuzhiyun case PERF_REG_RISCV_T0: 36*4882a593Smuzhiyun return "t0"; 37*4882a593Smuzhiyun case PERF_REG_RISCV_T1: 38*4882a593Smuzhiyun return "t1"; 39*4882a593Smuzhiyun case PERF_REG_RISCV_T2: 40*4882a593Smuzhiyun return "t2"; 41*4882a593Smuzhiyun case PERF_REG_RISCV_S0: 42*4882a593Smuzhiyun return "s0"; 43*4882a593Smuzhiyun case PERF_REG_RISCV_S1: 44*4882a593Smuzhiyun return "s1"; 45*4882a593Smuzhiyun case PERF_REG_RISCV_A0: 46*4882a593Smuzhiyun return "a0"; 47*4882a593Smuzhiyun case PERF_REG_RISCV_A1: 48*4882a593Smuzhiyun return "a1"; 49*4882a593Smuzhiyun case PERF_REG_RISCV_A2: 50*4882a593Smuzhiyun return "a2"; 51*4882a593Smuzhiyun case PERF_REG_RISCV_A3: 52*4882a593Smuzhiyun return "a3"; 53*4882a593Smuzhiyun case PERF_REG_RISCV_A4: 54*4882a593Smuzhiyun return "a4"; 55*4882a593Smuzhiyun case PERF_REG_RISCV_A5: 56*4882a593Smuzhiyun return "a5"; 57*4882a593Smuzhiyun case PERF_REG_RISCV_A6: 58*4882a593Smuzhiyun return "a6"; 59*4882a593Smuzhiyun case PERF_REG_RISCV_A7: 60*4882a593Smuzhiyun return "a7"; 61*4882a593Smuzhiyun case PERF_REG_RISCV_S2: 62*4882a593Smuzhiyun return "s2"; 63*4882a593Smuzhiyun case PERF_REG_RISCV_S3: 64*4882a593Smuzhiyun return "s3"; 65*4882a593Smuzhiyun case PERF_REG_RISCV_S4: 66*4882a593Smuzhiyun return "s4"; 67*4882a593Smuzhiyun case PERF_REG_RISCV_S5: 68*4882a593Smuzhiyun return "s5"; 69*4882a593Smuzhiyun case PERF_REG_RISCV_S6: 70*4882a593Smuzhiyun return "s6"; 71*4882a593Smuzhiyun case PERF_REG_RISCV_S7: 72*4882a593Smuzhiyun return "s7"; 73*4882a593Smuzhiyun case PERF_REG_RISCV_S8: 74*4882a593Smuzhiyun return "s8"; 75*4882a593Smuzhiyun case PERF_REG_RISCV_S9: 76*4882a593Smuzhiyun return "s9"; 77*4882a593Smuzhiyun case PERF_REG_RISCV_S10: 78*4882a593Smuzhiyun return "s10"; 79*4882a593Smuzhiyun case PERF_REG_RISCV_S11: 80*4882a593Smuzhiyun return "s11"; 81*4882a593Smuzhiyun case PERF_REG_RISCV_T3: 82*4882a593Smuzhiyun return "t3"; 83*4882a593Smuzhiyun case PERF_REG_RISCV_T4: 84*4882a593Smuzhiyun return "t4"; 85*4882a593Smuzhiyun case PERF_REG_RISCV_T5: 86*4882a593Smuzhiyun return "t5"; 87*4882a593Smuzhiyun case PERF_REG_RISCV_T6: 88*4882a593Smuzhiyun return "t6"; 89*4882a593Smuzhiyun default: 90*4882a593Smuzhiyun return NULL; 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun return NULL; 94*4882a593Smuzhiyun } 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif /* ARCH_PERF_REGS_H */ 97