1*4882a593Smuzhiyun i synthesize instructions events 2*4882a593Smuzhiyun b synthesize branches events (branch misses for Arm SPE) 3*4882a593Smuzhiyun c synthesize branches events (calls only) 4*4882a593Smuzhiyun r synthesize branches events (returns only) 5*4882a593Smuzhiyun x synthesize transactions events 6*4882a593Smuzhiyun w synthesize ptwrite events 7*4882a593Smuzhiyun p synthesize power events 8*4882a593Smuzhiyun o synthesize other events recorded due to the use 9*4882a593Smuzhiyun of aux-output (refer to perf record) 10*4882a593Smuzhiyun e synthesize error events 11*4882a593Smuzhiyun d create a debug log 12*4882a593Smuzhiyun f synthesize first level cache events 13*4882a593Smuzhiyun m synthesize last level cache events 14*4882a593Smuzhiyun t synthesize TLB events 15*4882a593Smuzhiyun a synthesize remote access events 16*4882a593Smuzhiyun g synthesize a call chain (use with i or x) 17*4882a593Smuzhiyun G synthesize a call chain on existing event records 18*4882a593Smuzhiyun l synthesize last branch entries (use with i or x) 19*4882a593Smuzhiyun L synthesize last branch entries on existing event records 20*4882a593Smuzhiyun s skip initial number of events 21*4882a593Smuzhiyun q quicker (less detailed) decoding 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun The default is all events i.e. the same as --itrace=ibxwpe, 24*4882a593Smuzhiyun except for perf script where it is --itrace=ce 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun In addition, the period (default 100000, except for perf script where it is 1) 27*4882a593Smuzhiyun for instructions events can be specified in units of: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun i instructions 30*4882a593Smuzhiyun t ticks 31*4882a593Smuzhiyun ms milliseconds 32*4882a593Smuzhiyun us microseconds 33*4882a593Smuzhiyun ns nanoseconds (default) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun Also the call chain size (default 16, max. 1024) for instructions or 36*4882a593Smuzhiyun transactions events can be specified. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun Also the number of last branch entries (default 64, max. 1024) for 39*4882a593Smuzhiyun instructions or transactions events can be specified. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun Similar to options g and l, size may also be specified for options G and L. 42*4882a593Smuzhiyun On x86, note that G and L work poorly when data has been recorded with 43*4882a593Smuzhiyun large PEBS. Refer linkperf:perf-intel-pt[1] man page for details. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun It is also possible to skip events generated (instructions, branches, transactions, 46*4882a593Smuzhiyun ptwrite, power) at the beginning. This is useful to ignore initialization code. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun --itrace=i0nss1000000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun skips the first million instructions. 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun The 'e' option may be followed by flags which affect what errors will or 53*4882a593Smuzhiyun will not be reported. Each flag must be preceded by either '+' or '-'. 54*4882a593Smuzhiyun The flags are: 55*4882a593Smuzhiyun o overflow 56*4882a593Smuzhiyun l trace data lost 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun If supported, the 'd' option may be followed by flags which affect what 59*4882a593Smuzhiyun debug messages will or will not be logged. Each flag must be preceded 60*4882a593Smuzhiyun by either '+' or '-'. The flags are: 61*4882a593Smuzhiyun a all perf events 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun If supported, the 'q' option may be repeated to increase the effect. 64