1*4882a593SmuzhiyunC SB+fencembonceonces 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun(* 4*4882a593Smuzhiyun * Result: Never 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This litmus test demonstrates that full memory barriers suffice to 7*4882a593Smuzhiyun * order the store-buffering pattern, where each process writes to the 8*4882a593Smuzhiyun * variable that the preceding process reads. (Locking and RCU can also 9*4882a593Smuzhiyun * suffice, but not much else.) 10*4882a593Smuzhiyun *) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun{} 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunP0(int *x, int *y) 15*4882a593Smuzhiyun{ 16*4882a593Smuzhiyun int r0; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun WRITE_ONCE(*x, 1); 19*4882a593Smuzhiyun smp_mb(); 20*4882a593Smuzhiyun r0 = READ_ONCE(*y); 21*4882a593Smuzhiyun} 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunP1(int *x, int *y) 24*4882a593Smuzhiyun{ 25*4882a593Smuzhiyun int r0; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun WRITE_ONCE(*y, 1); 28*4882a593Smuzhiyun smp_mb(); 29*4882a593Smuzhiyun r0 = READ_ONCE(*x); 30*4882a593Smuzhiyun} 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunexists (0:r0=0 /\ 1:r0=0) 33