1*4882a593SmuzhiyunC LB+fencembonceonce+ctrlonceonce 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun(* 4*4882a593Smuzhiyun * Result: Never 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This litmus test demonstrates that lightweight ordering suffices for 7*4882a593Smuzhiyun * the load-buffering pattern, in other words, preventing all processes 8*4882a593Smuzhiyun * reading from the preceding process's write. In this example, the 9*4882a593Smuzhiyun * combination of a control dependency and a full memory barrier are enough 10*4882a593Smuzhiyun * to do the trick. (But the full memory barrier could be replaced with 11*4882a593Smuzhiyun * another control dependency and order would still be maintained.) 12*4882a593Smuzhiyun *) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun{} 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunP0(int *x, int *y) 17*4882a593Smuzhiyun{ 18*4882a593Smuzhiyun int r0; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun r0 = READ_ONCE(*x); 21*4882a593Smuzhiyun if (r0) 22*4882a593Smuzhiyun WRITE_ONCE(*y, 1); 23*4882a593Smuzhiyun} 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunP1(int *x, int *y) 26*4882a593Smuzhiyun{ 27*4882a593Smuzhiyun int r0; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun r0 = READ_ONCE(*y); 30*4882a593Smuzhiyun smp_mb(); 31*4882a593Smuzhiyun WRITE_ONCE(*x, 1); 32*4882a593Smuzhiyun} 33*4882a593Smuzhiyun 34*4882a593Smuzhiyunexists (0:r0=1 /\ 1:r0=1) 35