1*4882a593Smuzhiyun #ifndef _ASM_X86_DISABLED_FEATURES_H 2*4882a593Smuzhiyun #define _ASM_X86_DISABLED_FEATURES_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* These features, although they might be available in a CPU 5*4882a593Smuzhiyun * will not be used because the compile options to support 6*4882a593Smuzhiyun * them are not present. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This code allows them to be checked and disabled at 9*4882a593Smuzhiyun * compile time without an explicit #ifdef. Use 10*4882a593Smuzhiyun * cpu_feature_enabled(). 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_X86_SMAP 14*4882a593Smuzhiyun # define DISABLE_SMAP 0 15*4882a593Smuzhiyun #else 16*4882a593Smuzhiyun # define DISABLE_SMAP (1<<(X86_FEATURE_SMAP & 31)) 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #ifdef CONFIG_X86_UMIP 20*4882a593Smuzhiyun # define DISABLE_UMIP 0 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun # define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifdef CONFIG_X86_64 26*4882a593Smuzhiyun # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) 27*4882a593Smuzhiyun # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) 28*4882a593Smuzhiyun # define DISABLE_CYRIX_ARR (1<<(X86_FEATURE_CYRIX_ARR & 31)) 29*4882a593Smuzhiyun # define DISABLE_CENTAUR_MCR (1<<(X86_FEATURE_CENTAUR_MCR & 31)) 30*4882a593Smuzhiyun # define DISABLE_PCID 0 31*4882a593Smuzhiyun #else 32*4882a593Smuzhiyun # define DISABLE_VME 0 33*4882a593Smuzhiyun # define DISABLE_K6_MTRR 0 34*4882a593Smuzhiyun # define DISABLE_CYRIX_ARR 0 35*4882a593Smuzhiyun # define DISABLE_CENTAUR_MCR 0 36*4882a593Smuzhiyun # define DISABLE_PCID (1<<(X86_FEATURE_PCID & 31)) 37*4882a593Smuzhiyun #endif /* CONFIG_X86_64 */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS 40*4882a593Smuzhiyun # define DISABLE_PKU 0 41*4882a593Smuzhiyun # define DISABLE_OSPKE 0 42*4882a593Smuzhiyun #else 43*4882a593Smuzhiyun # define DISABLE_PKU (1<<(X86_FEATURE_PKU & 31)) 44*4882a593Smuzhiyun # define DISABLE_OSPKE (1<<(X86_FEATURE_OSPKE & 31)) 45*4882a593Smuzhiyun #endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #ifdef CONFIG_X86_5LEVEL 48*4882a593Smuzhiyun # define DISABLE_LA57 0 49*4882a593Smuzhiyun #else 50*4882a593Smuzhiyun # define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31)) 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #ifdef CONFIG_PAGE_TABLE_ISOLATION 54*4882a593Smuzhiyun # define DISABLE_PTI 0 55*4882a593Smuzhiyun #else 56*4882a593Smuzhiyun # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) 57*4882a593Smuzhiyun #endif 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #ifdef CONFIG_RETPOLINE 60*4882a593Smuzhiyun # define DISABLE_RETPOLINE 0 61*4882a593Smuzhiyun #else 62*4882a593Smuzhiyun # define DISABLE_RETPOLINE ((1 << (X86_FEATURE_RETPOLINE & 31)) | \ 63*4882a593Smuzhiyun (1 << (X86_FEATURE_RETPOLINE_LFENCE & 31))) 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #ifdef CONFIG_RETHUNK 67*4882a593Smuzhiyun # define DISABLE_RETHUNK 0 68*4882a593Smuzhiyun #else 69*4882a593Smuzhiyun # define DISABLE_RETHUNK (1 << (X86_FEATURE_RETHUNK & 31)) 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #ifdef CONFIG_CPU_UNRET_ENTRY 73*4882a593Smuzhiyun # define DISABLE_UNRET 0 74*4882a593Smuzhiyun #else 75*4882a593Smuzhiyun # define DISABLE_UNRET (1 << (X86_FEATURE_UNRET & 31)) 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #ifdef CONFIG_IOMMU_SUPPORT 79*4882a593Smuzhiyun # define DISABLE_ENQCMD 0 80*4882a593Smuzhiyun #else 81*4882a593Smuzhiyun # define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Make sure to add features to the correct mask 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define DISABLED_MASK0 (DISABLE_VME) 88*4882a593Smuzhiyun #define DISABLED_MASK1 0 89*4882a593Smuzhiyun #define DISABLED_MASK2 0 90*4882a593Smuzhiyun #define DISABLED_MASK3 (DISABLE_CYRIX_ARR|DISABLE_CENTAUR_MCR|DISABLE_K6_MTRR) 91*4882a593Smuzhiyun #define DISABLED_MASK4 (DISABLE_PCID) 92*4882a593Smuzhiyun #define DISABLED_MASK5 0 93*4882a593Smuzhiyun #define DISABLED_MASK6 0 94*4882a593Smuzhiyun #define DISABLED_MASK7 (DISABLE_PTI) 95*4882a593Smuzhiyun #define DISABLED_MASK8 0 96*4882a593Smuzhiyun #define DISABLED_MASK9 (DISABLE_SMAP) 97*4882a593Smuzhiyun #define DISABLED_MASK10 0 98*4882a593Smuzhiyun #define DISABLED_MASK11 (DISABLE_RETPOLINE|DISABLE_RETHUNK|DISABLE_UNRET) 99*4882a593Smuzhiyun #define DISABLED_MASK12 0 100*4882a593Smuzhiyun #define DISABLED_MASK13 0 101*4882a593Smuzhiyun #define DISABLED_MASK14 0 102*4882a593Smuzhiyun #define DISABLED_MASK15 0 103*4882a593Smuzhiyun #define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP| \ 104*4882a593Smuzhiyun DISABLE_ENQCMD) 105*4882a593Smuzhiyun #define DISABLED_MASK17 0 106*4882a593Smuzhiyun #define DISABLED_MASK18 0 107*4882a593Smuzhiyun #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #endif /* _ASM_X86_DISABLED_FEATURES_H */ 110